Memory built-in self-test

The memories used in the SAMPA are dual and single port 8-transistor Static Random Access Memory (SRAM)IPs provided byARM[53]. MemoryIPsare used for their higher memory densities, lower power, ease of design and for their proven design. The IPs that are used do not provide BIST for testing of manufacturing

defects, so a custom built-in memory test has been designed to provide quick pass/fail testing.

The test structure is built as a wrapper surrounding eachIP, where the data, address, and control lines for the memories are multiplexed between the normal data path and the test structure. The test is initiated by pulling a pin high ex-ternally to the chip.

The algorithm used for testing is a 5N length test (3N for dual port memory), where N is the number of addresses. Meaning it takes this amount of clock cycles to complete a loop and completely verify a memory. The test will loop continuously as long as the test is enabled, providing the added possibility to also use the test for evaluating the memories’ Single Event Upset (SEU) probability in a irradiation test.

The test is based on writing a fixed pattern, in this case a checkerboard pattern, of 0x2AA to the memory in the first iteration, then in the next iteration it will read and check the 0x2AA pattern and write back a pattern of 0x155 (the inverse pattern) and in the next it will check the 0x155 and write 0x2AA and so on [54].

The test algorithm is similar to the Modified Algorithm Test Sequence (MATS) march algorithm [55]. The algorithms are normally only designed for single port memories, but for testing of the dual port memories, it can be simplified, as they are in the current design always written on one side and read on the other. Thus, it is possible to do the read and write in the same cycle, though not at the same address, so the write is always lagging one address behind the read.

When an address in the memory is read out and it contains an incorrect value, the test structure will set a signal high for one clock cycle indicating an error. The signals indicating an error from each of the test structures are ORed together to provide a combined output signal. Externally to the device, there are two status outputs available, a latched single-ended output, and a pulsed differential output.

The pulsed output will give one pulse per address where an error is found on, while the latched output will stay high until an error is found and will then stay low, enabling a slower test system to detect an error without the need to sample the pulsed output at a high speed. The latched output is primarily intended for production testing, while the pulsed output can for instance be used for SEU detection during radiation testing.

The minimum running time for one test iteration is determined by the largest

memory that runs on the slowest clock, which is the pedestal memory. The decision on which test to implement is a trade-off between test time and fault coverage. The 5N chequerboard sequence that is implemented does not provide a full coverage of all possible errors, but is fast, requiring only 256 µs when operated with input clocks of 320 MHz and 20 MHz for the serial clock andADCclock respectively.

The chequerboard tester implemented is primarily able to detect:

Stuck-at faults A stuck-at fault occurs when the value of a cell or line is always 0 (a stuck-at-0 fault) or always 1 (a stuck-at-1 fault).

Stuck-open faults The connection to a cell is broken returning the previous read value.

Address decoding faults Faults present in the address decoding logic. This in-cludes failure to access a cell located at an address, shorts between addresses, stuck-at address lines, and stuck-open address lines.

However, it is not able to, or only partly able to detect:

Coupling faults A write to one cell changes the content of a second cell. This includes a transition in one cell that inverts another cell, a transition in one cell that forces a 0 or 1 in the other cell, and state coupling faults where a cell is only forced to a value if the coupling cell is in a certain state. Only a fraction of these can reliably be detected with the currently used test algorithm.

Transition faults A cell or line fails to undergo a transition from 0 to 1 or 1 to 0.

Data retention faults When the cell is unable to hold its value. InSRAMthis could be caused by defective pull-ups. Data retention is tested by adding a delay after the normal sequence is done and then continue after the delay.

As the SAMPA does not rely particularly on a long retention time in the memory, this was not added in the automatic test. On the other hand, it would be possible to test this by stopping the clocks to the SAMPA for a while before enabling them again.

Read disturb fault Reading the cell multiple times will flip its content. Multiple reads on the same cell are not done with the current algorithm.

A more common industry technique is to use a 13N algorithm as with the Inductive Fault Analysis (IFA) algorithm [56] or a 14N as with March SRD [54]

for complete coverage. Full coverage for the previously mentioned techniques is only valid for memories with individual cell access. Word-orientedSRAM, where a complete word is read and written at once, introduces the problem of state coupling faults between two cells at one address. To detect these faults all four state transitions between two cells must be tested. This would be done by running the same test with different patterns. For a 10-bit memory like in the SAMPA, this would require five iterations of the algorithm [56], significantly increasing test time. Coupling coverage could have been a bit better if the true physical layout of the cells in a word would have been known so that the chequerboard pattern is represented in the actual layout.

For using the pulsed output from the device forSEUdetection, there are some considerations;

• Multiple changed bits in the same address are only detected as one error.

• All the memory tests are run in parallel with the error outputs ORed toget-her, so if two memory testers discover an error at the same time, they will mask each other.

• The pulse length for a found error is one clock cycle of the clock domain the memory tester is running at. If an error is found in two or more consecutive addresses, the error signal from those addresses will be conjoined.

All of this will add to the dead time of the system as well as the uncertainty in the total number of errors found.

A possible extension to theBISTis to make it controllable through theJTAG. This would provide the possibility to supply different patterns to the tester, which would cover testing of more coupling faults. By adding some extra complexity, it would be possible to make the algorithm programmable. The default simple test would then provide enough detection of faults before packaging, while the extended testing could be done post-packaging if a higher fault detection was required.