Significant parameters in characterizing a flip-flop’s performance are its delay time and power dissipation. An optimal flip-flop design has low power consumption, imposes no delay and gives a valid output at all time. Trade-offs between these parameters must be done in practical implementation.
3.2.1 Timing and Delay
For estimating the performance of a flip-flop, three important timings and delays are used: (1) propagation delay, (2) setup time and (3) hold time.
Setup and hold time define the relationship between the clock and input data, while the propagation delay defines the relationship between the internal delay for the input signal to propagate through the flip-flop and change the output signal.
The total delay of a sequencing element can be expressed as the time from the input signal changes its state to the output signal is stabilized.
A flip-flop can capture an input signal even though it arrives later than the setup time, but the propagation delay might increase, resulting in a large total delay[29].
Propagation Delay
The propagation delay of a flip-flop is defined as its clock-to-output delay.
This equals the maximum delay from the arrival of the clock’s active edge
to the output of the flip-flop is considered stable. Usually the propagation delay differs from low to high transition and high to low transition. By definition, the delay is the maximum value of these two delay:
tpcq=max tpcqLH,tpcqH L
(3.2) Clock Contamination Delay
The clock contamination delay is the minimum time from the clock changes to the output is available that occurs when the data input arrives early.
I.e. the time it takes from the clock goes high to a valid output signal is available.
tccq=max tccqLH,tccqH L
(3.3)
Setup Time
The input must be stable for some time before the flip-flop triggers at the clock edge. The setup time is defined as the time the data value must remain stable around the arrival of the clock’s active edge to ensure that the flip-flop retains the proper output value.
The setup time may differ for a low-to-high and high-to-low transition.
Setup time is by definition the maximum of these values:
tsetup=max tsetup,LH,tsetup,HL
(3.4) Hold Time
After the clock signal has changed, the input must be hold for a period of time to allow the signal to propagate through the flip-flop for ensuring a stable output. This delay time is called hold time. The hold time may be negative, which means that the input signal may change before the clock changes and still ensuring the proper output value. As for other timing measurements, the hold time may differ for a low-to-high and high-to-low transition. The hold time is defined as:
thold= max(thold,LH,thold,HL) (3.5) Total Delay
The delay of a flip-flop can be expressed as the time taken from the input changes its state to the output has stabilized. The total delay can be expressed as tdelay = tsetup+tpcq, where tsetup is the time taken for the input to propagate and stabilize in the flip-flop, andtpcqis the time taken from the clock goes high to a valid outputQis available.
0.030 0.035 0.04 0.045 0.05 0.055 0.06 0.02
0.04 0.06 0.08 0.1 0.12 0.14
tDC (ns) tdelay (ns)
tCQ−up tCQ−down tDQ−up tDQ−down tDQ−min
Figure 3.4: PowerPC 603 flip-flop:tdelayvstsetup
In Fig.3.4simulation oftdelayvs.tsetuphas been done atVDD=200 mV.
It is clearly shown how the delay is directly dependent on the time the input signal arrives in relationship to the clock signal. At the left side of the plot, the input signal exceeds the clock edge, and the output is not valid. At the right side the output signal monolithically grows due to increasedtsetup.
3.2.2 Power Consumption
A common method for measuring the power consumption of a flip-flop is to operate the flip-flop at maximum operating frequency with a maximum power consumption pattern applied on the input. The power consumption is then measured as the average supply current drawn by the flip-flop with input buffers and some load taken into account.
The average power consumptionPcan be defined:
P=iVDDavg·VDD (3.6)
whereiVDDavg is the average current drawn from the power supply by the circuit over the time being measured andVDDis the power supply voltage.
3.2.3 Performance Metrics Power-Delay Product
Both power and delay are metrics which can be adjusted individually.
Therefore they are usually not considered as good figure-of-merits for a design or circuit. The Power-Delay Product (PDP) is the product of delay time and power consumption, taking both metrics into account. PDP is considered a good figure of merit for a circuit’s performance.
PDP is calculated as:
PDP=tdelay·P (3.7)
wheretdelayis the delay found in Sec.3.2.1andPis the power consumption, as defined in Sec.3.2.2.
Energy-Delay Product
The Energy-Delay Product (EDP) weights the execution time more than PDP. EDP is considered a relatively implementation neutral metric, causing architectural improvements contributing most to both performance and energy efficiency to stand out [41].
EDP can be expressed as:
EDP= PDP·tdelay=tdelay·tdelay·P (3.8) where PDP is the Power-Delay Product found in Sec. 3.2.3, tdelay is the delay found in Sec. 3.2.1and P is the power consumption, as defined in Sec.3.2.2.
3.2.4 Metastability
A flip-flop is abistable device, meaning it has two stable states (0 and 1).
The binary decision which the flip-flop must take to set the output can take an unbounded amount of time in the case of colliding inputs [42].
When a flip-flop experience this, it is said to be in ametastable state where the output is at an indeterminate level between 0 and 1 [29].
When the output of a flip-flop in a metastable state is sampled by other digital circuitry, non-binary signals will propagate through the binary systems. This effect is called asynchronization failure.
Metastable states cannot be totally avoided when designing a systems, but the probability of occurrence can be made reasonably small with careful consideration of timing.