The capacitive precharge NP domino carry circuit, which will be named CPULVC, is a carry circuit based on the ULV5 logic style presented in [14].
The CPULVC is created in an effort to make a simpler and more reliable circuit by utilizing capacitive division to implement the carry logic. The idea is to let the capacitive division between three equal size capacitors handle the logic of the circuit as shown in Table 3.3.1(page 46).
Figure 3.3.1: Schematic: ULV5 carry N-type circuit. Figure 3.3.2: Schematic: ULV5 carry P-type circuit.
The A and B input needs to be either a rising or a falling edge signal generated by a level-to-edge converter to get a full transition both ways, or an output from a logic style like the ULV2[5] providing a transition of Vdd/2 both ways. A level-to-edge converter suitable for this purpose is proposed in section 3.4.2.1.
If both 𝑨� and 𝑩� in the N-type circuit are rising edge signals, a carry output transition is triggered instantly due to a voltage increase of ~2/3Vdd on the En floating gate (Figure 3.3.1) making it stronger than the Pp precharge transistor and independent of the carry signal. The output is also independent of the carry input when both 𝑨� and 𝑩� are falling and thereby reducing the voltage on the floating gate by ~2/3Vdd. This turns off the En transistor and makes the ~1/3Vdd voltage rise Cin is able to produce insignificant. For the case where 𝑨� and 𝑩� are contrasting, the two signals will cancel each other and leave the circuit working as a
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ULV5 inverter with the 𝑪𝑪𝑪����� signal as input, although the gate delay is slightly higher because the capacitive division will reduce the floating gate voltage swing.
Carry truth table N-type signals P-type signals A B Cin Cout 𝐴̅ 𝐵� 𝐶𝐶𝑛����� Cout A B Cin Cout’
0 0 0 0 ↑ ↑ ↑ ↓ ↓ ↓ ↓ ↑
0 0 1 0 ↑ ↑ 0 ↓ ↓ ↓ 1 ↑
0 1 0 0 ↑ ↓ ↑ ↓ ↓ ↑ ↓ ↑
0 1 1 1 ↑ ↓ 0 1 ↓ ↑ 1 0
1 0 0 0 ↓ ↑ ↑ ↓ ↑ ↓ ↓ ↑
1 0 1 1 ↓ ↑ 0 1 ↑ ↓ 1 0
1 1 0 1 ↓ ↓ ↑ 1 ↑ ↑ ↓ 0
1 1 1 1 ↓ ↓ 0 1 ↑ ↑ 1 0
Table 3.3.1: Precharge NP domino capacitive divider carry logic.
The P-type circuit is designed in a manner complementary to the N-type, still using capacitive division to achieve the desired logic result but using a precharge level of ‘0’ and keeping the output unchanged in the evaluation phase in the case of a carry and producing a rising edge in the case of no carry. Hence the signal produced by the P-type circuit is in the form needed for the N-type circuit as the N-type output is in the form needed for the P-type circuit. This is shown in Table 3.3.1.
The circuit has been scaled for a 300mV supply voltage and the strength of the PMOS transistor has only been increased using fingers to reduce the impact of changes to the Vdd.
With a supply voltage of 300mV the circuit is able to process 64 bits in one clock cycle as shown in Figure 3.3.3 despite problems with output drifting that can be seen in both Figure 3.3.3 and Figure 3.3.4, which is an attribute commonly associated with dynamic logic.
Figure 3.3.3: Simulation: 64 bit ULV5 n-p domino carry chain, propagating ‘0’.
47 The propagating ‘0’ simulation in Figure 3.3.3 is based on the conditions in Equation 3.2.2 on page 42. Accordingly the simulation conditions in Figure 3.3.4 are the same as in Equation 3.2.1.
To increase stability the number of bits per clock cycle can be reduced together with a higher clock frequency. The cost of this is a slight reduction of average speed per bit, caused by flip-flop setup time overhead and slower carry propagation for the LSBs.
The CPULVC has been analyzed and compared to the traditional CMOS carry circuit in terms of delay, power, PDP and EDP. The results are presented in Table 3.3.2 and shows that the CPULVC is 6 times faster than the standard CMOS at 300mV achieved without increasing the power consumption more than two times. The PDP of the SULVC is therefore 3 times better at 300mV but the SULVC also has a 2.6 times better PDP than the conventional CMOS carry circuit running at PDP-optimal supply voltage.
Because of the good delay characteristics of the SULVC at low voltage the EDP is 18 times higher than traditional CMOS running at 300mV. However the traditional carry circuit is able to achieve a 40% lower EDP at its EDP-optimal supply voltage.
Std. CMOS CPULVC Delay @ 300mV 20.5ns 3.5ns Power @ 300mV 10.4nW 19.26nW PDP @ 300mV 212.3aJ
64.4aJ Optimal PDP 165.9aJ
EDP @ 300mV 4.35yJs
0.236yJs Optimal EDP 0.1486yJs
Table 3.3.2: CPULVC performance analysis.
Figure 3.3.4: Simulation: 64 bit ULV5 n-p domino carry chain, “propagating” ‘1’.
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The CPULVC can therefore be a good choice for systems where it is important to get as much data as possible processed for a certain amount of energy because of its low PDP. It is also a better choice than the conventional CMOS carry circuit, both EDP and PDP wise in low-voltage systems.
Advantages Disadvantages
• Good PDP.
• EDP ok for low-voltage domain.
• Limited logic depth due to drifting.
Experiments using 4 input capacitors with two chains in parallel to create a partially differential topology were also conducted yielding marginally better stability at the cost of a substantial decrease in delay due to the extra capacitor in the capacitive division on the floating gate. A fully differential version has also been developed in collaboration with another master student.
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