Design of Measurement Board for Dynamic Impedance Measurements on Envelope Tracking Amplifiers

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NTNU Norwegian University of Science and Technology Faculty of Information Technology and Electrical Engineering Department of Electronic Systems

Eirik Hovde Skanke

Design of Measurement Board for Dynamic Impedance Measurements on Envelope Tracking Amplifiers

Master’s thesis in Electronic Systems Design Supervisor: Morten Olavsbråten

March 2021

Master ’s thesis

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Eirik Hovde Skanke

Design of Measurement Board for

Dynamic Impedance Measurements on Envelope Tracking Amplifiers

Master’s thesis in Electronic Systems Design Supervisor: Morten Olavsbråten

March 2021

Norwegian University of Science and Technology

Faculty of Information Technology and Electrical Engineering Department of Electronic Systems

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Abstract

This thesis presents the design of a measurement board (officially namedIVm Board) intended for dynamic current and voltage measurements between an envelope tracker and an RFPA. New methods for design and measurements are proposed to increase the performance and to obtain the optimal circuit parameters which satisfies the design criteria for bandwidth and power limitations.

In addition, a bias tee circuit is designed in order to measure the IVm Board when applying DC bias voltages. The measurement setup is specified to maintain measurement integrity, and thus also the accuracy of the IVm Board characterization.

The IVm Board PCB is captured in Altium Designer. Op-amp datasheets are used to design the amplifier circuits. Signal- and power integrity methods are applied to ensure good circuit performance. S-parameter simulations in ADS provide the component values which yield the best frequency responses, stability and low power dissipation. Properties like common-mode rejection and resistor tolerance are also assessed through simulations. The Bias Tee is designed using SimSurfing and ADS, and the PCB is captured in Altium Designer.

Methods for measurements and calibrations are presented. A two-port VNA is used to measure S-parameters. The IVm Board, biased through the Bias Tee, is measured with the proposed methods in an initial and flipped condition for polarity assessment. A conventional measurement method through oscilloscope verifies the VNA measurements of the IVm Board. The Bias Tee is measured with a VNA in several runs to obtain all the port combinations.

The measured, qualitative Bias Tee bandwidth is about2 GHz. The gains in the stop-bands increase about two decades earlier compared with the simulated responses. VNA- and scope measurements on the IVm Board are in agreement. The voltage measurement circuit yields perfectly flat gain up to200 MHz. The current measurement circuit marks a15 dBgain drop in the pass-band compared with simulations. Flipping the IVm Board yields correct frequency responses compared to simulations, with a marginal200 MHzbandwidth. It is observed that changes in frequency responses due to bias voltages are negligible.

The methods have proven to characterize the IVm Board successfully. The Bias Tee is biasing the IVm Board with minimal influences. From measurements, the IVm Board is proved to be invariant of strong biasing, thus, indicating good common-mode rejection. The most important outcome from the measurements is the fact that IVm Board is very sensitive to high resistance tolerances, as flipping the IVm Board yields correct frequency response. The IVm Board is concluded to be a semi-successful prototype design, as a result from the proposed methods.

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Sammendrag

Denne hovedoppgaven presenterer et målekortdesign (offisielt kaltIVm Board) myntet på dy- namiske strøm- og spenningsmålinger mellom en envelope tracker og en RFPA. Nye design- og målemetoder er foreslått for å øke ytelsen og for å oppnå optimale kretsparametere som oppfyller designkriteriene for båndbredde og effektbegrensninger. I tillegg er enbias tee-krets designet for å kunne måle IVm Board når DC-forspenninger påtrykkes. Måleoppsettet er spesifisert for å overholde integriteten til målinger og derfor også nøyaktigheten til karakteriseringen av IVm Board.

Kretskortet til IVm Board er tegnet i Altium Designer. Op-amp datablad er brukt for å konstruere forsterkerkretsene. Teknikker for å sikre god signal- og kraftintegritet er praktisert. Simulering av S-parametere i ADS finner komponentverdiene som gir de beste frekvensresponsene, stabilitet og lavt effektforbruk. Egenskaper somcommon-mode rejectionog motstandstoleranse er også vurdert gjennom simuleringer. Bias Tee er designet ved bruk av SimSurfing og ADS, og kretskortet er tegnet i Altium Designer.

Måle- og kalibreringsmetoder er presentert. En to-ports VNA er brukt for å måle S-parametere.

IVm Board, forspent gjennom Bias Tee, er målt med den foreslåtte målemetodikken for initiell og flippet tilstand, for polaritetsvurdering. En konvensjonell målemetode via oscilloskop verifiserer VNA-målingene av IVm Board. Bias Tee er målt med en VNA i flere runder for å oppnå alle portkombinasjoner.

Den målte, kvalitative båndbredden til Bias Tee er omtrent 2 GHz. Forsterkningene i stopp- båndene øker omtrent to dekader tidligere sammenlignet med simulerte reponser. VNA- og skopmålinger på IVm Board viser enighet. Spenningmålekretsen oppnår perfekt flat forsterkning opp til200 MHz. Strømmålekretsen markerer et forsterkningsfall på 15 dB i passbåndet sammenlignet med simuleringer. Snur man IVm Board oppnås riktig frekvensrespons sammenlignet med simuleringer, men en marginal båndbredde på 200 MHz. Det observeres at endringer i frekvensresponser pga. forspenninger er neglisjerbare.

Metodene viser at IVm Board kan karakteriseres riktig. Bias Tee leverer forspenning til IVm Board med lite påvirkninger. Målinger beviser at IVm Board er upåvirkelig av sterk forspenning, og dermed en indikasjon på godcommon-mode rejection. Det viktigste utfallet fra målingene er det faktum at IVm Board er veldig sensitiv til høye motstandstoleranser, siden en snudd IVm Board gir korrekt frekvensrespons. IVm Board konkluderes som et halvt suksessfullt prototypedesign, som et resultat av de foreslåtte metodene.

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Acknowledgement

This thesis is submitted in partial fulfillment of the requirements for the degree of Master of Science (MSc) at Department of Electronic Systems (IES), Norwegian University of Science and Technology (NTNU) in Trondheim, Norway.

I want to express my personal thank you to my supervisor Morten Olavsbråten, for several reasons. Firstly, for introducing me to this very intriguing project, with formidable enthusiasm as always. It has positively affected my motivation of working thoroughly on this thesis. Secondly, for being very open-minded and enjoyable to work with – a good quality for a supervisor to possess. Every meeting has refreshed my outlook of the project work. Lastly, and probably the most important reason, is the fact that he has been carrying all the measurements in this thesis.

You may ask yourself: why? Take a look at the submission date, and you will know why. At the date of submission it has been over a year since the global COVID-19 pandemic began. It is no secret that the pandemic has put restrictions on the society in general. As a master student, this tremendously reduced the practicalities of conducting measurements by myself. I am therefore sincerely grateful.

Eirik Hovde Skanke Trondheim, 2021-03-30

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List of Figures

2.1 The configuration for the inverting op-amp and the non-inverting op-amp . . . . 3

2.2 Small signal frequency responses . . . 4

2.3 Op-amp configured as a difference amplifier. . . 5

2.5 The in-amp with source, load, sensing, voltage division and matching resistors. . . 8

2.6 IC package thermal metrics . . . 8

2.7 Two-port network and its scattering parameters illustrated. . . 10

2.8 Simple bias tee circuit . . . 11

3.1 Printed circuit board (PCB) of the predecessing prototype. . . 13

3.2 Isometric view of IVm Board v0.2.0. . . 14

3.3 IVm Board between the tracker source and the RF power amplifier (RFPA) drain. . 15

3.4 Compiled schematic in Altium Designer for the in-amp. . . 17

3.5 MLCC reactances and DC bias capacitances . . . 18

3.7 Four-port configuration of the IVm Board. . . 20

3.8 Bode plot of the in-amp frequency response . . . 22

3.9 The harmonic balance simulation of the in-amp. . . 24

3.10 Isometric drawing of the Bias Tee and the semi-assembled PCB . . . 24

3.11 The Advanced Design System (ADS) schematic of Bias Tee v0.1.0. . . 26

3.12 Bias Tee currents. . . 26

3.13 In-amp frequency response when Bias Tee is incorporated . . . 27

4.1 Rohde & Schwarz ZNB 8 vector network analyzer (VNA) . . . 29

4.2 SMA-adapter . . . 30

4.3 Illustration of the measurement setup for oscilloscope measurements. . . 32

4.4 Probing theVREFpin on IVm Board when conducting scope measurements . . . . 33

5.1 S-parameter measurements of Bias Tee with ferrite bead or0 Ωresistor. . . 35

5.2 S-parameter measurements of Bias Tee vs. simulations. . . 36

5.3 Scope, VNA and simulated response of the voltage measurement op-amp . . . 37

5.4 VNA measurements of the in-amp, biased with 5V and 25 V . . . 37

5.5 VNA measurements of the flipped in-amp . . . 38

5.6 VNA measurements of the flipped in-amp with different bias voltages . . . 38

5.7 Scope measurement of the flipped in-amp . . . 39

5.8 Scope measurement of the in-amp . . . 39

5.9 Scope measurement of the flipped in-amp . . . 39

5.10 Measured output impedance (magnitude) on P3 and P4. . . 40

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List of Tables

3.1 IVm Board Specifications . . . 14 3.2 The components in the Bias Tee. . . 25

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Glossary

Altium Designer is an EDA tool for schematic capture and PCB design. ix, 16–19, 25, 45

Bias Tee is the proper noun for the bias tee designed in this project. 2, 24, 29–31, 33–36, 41–43, 45 CF op-amp is a current feedback (CF) op-amp. 6

e.g. "for example". 10, 16, 17, 21, 31, 33, 43, 45

heat sink is a passive device which transfers heat from a thermal conducting body to e.g. air. 19, 20, 31 i.e. "that is". 4–7, 20, 21, 24, 26, 30, 31, 40, 41, 43

in-amp is an instrumentation amplifier. ix, 3, 5–8, 15–17, 20–24, 27, 31, 37–40, 42, 43, 45

IVm Board is the official name for the current- and voltage measurement board in this project. ix, 1, 2, 13–18, 20, 21, 23–26, 29–31, 33, 37, 38, 40–43, 45, 46

Murata is a Japanese manufacturer of electronic components. xi, 17, 24, 25 op-amp is an operational amplifier. ix, xi, 2–6, 14–22, 37, 42, 46

P Spice is a SPICE-based simulator by Cadence Design Systems. 20 PathWave ADS is a microwave EDA tool by Keysight. 1, 13, 20

pole is a transfer function’s cut-off frequency, e.g. in an RC circuit. 19

signal integrity describes the quality of a received electrical signal, compared to the transmitted signal. xiii, 13, 42

SimSurfing is an online design support tool by Murata. 18, 24, 25

SMA is a coaxial connector of of the type "SubMiniature version A". ix, 16, 29, 30, 33 Texas Instruments is a global semiconductor design and manufacturing company. 6, 20

tracker is a bias source which applies ET on the output. ix, 15, 29, 43

xi

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Acronyms

ADS Advanced Design System. ix, xi, 1, 13, 20, 21, 24–26, 36, 41, 42, 45

AWG arbitrary waveform generator. 31 BOM bill of materials. 14, 16, 17 CF current feedback. xi, 6

CMRR common-mode rejection ratio. 4, 6, 7, 15, 23

DUT device under test. 9, 10

ESR equivalent series resistance. 17, 26 ET envelope tracking. xi, 1, 14, 41, 46 FET field effect transistor. 6, 7 GBWP gain-bandwidth product. 6 GCPW grounded coplanar waveguide. 19 IC integrated circuit. 8

MLCC multi-layer ceramic capacitor. 17, 18

PCB printed circuit board. ix, 1, 2, 13–20, 23–25, 33, 45

PI power integrity. 13, 17

RF radio frequency. ix, xiii, 1, 14, 25, 29, 41, 46

RFPA RF power amplifier. ix, 1, 14, 15, 18, 29, 31, 41, 43, 46

SI signal integrity. 13, 16, 23, 42 SNR signal-to-noise ratio. 7

SOIC small outline integrated circuit. 19 SOLT short-open-load-through. 10, 29 SRF self resonant frequency. 17 TH through hole. 17, 18 TL transmission line. 16, 19, 42 TOSM through-open-short-match. 10

VNA vector network analyzer. ix, 10, 24, 29–31, 33, 34, 37–39, 41

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1 Introduction

„

The beginning is the most important part of the work.

—Plato Philosopher

The efficiency of an RF power amplifier (RFPA) is highly important in the wireless systems today.

There are many architectures for improving the efficiency of an RFPA. One of the methods is envelope tracking (ET). In this method the supply voltage (drain voltage) of the RFPA is analogous with the envelope of the signal the RFPA amplifies. One of the challenges of this is to measure the dynamic currents and voltages applied to the RFPA at drain and gate (if gate tracking is implemented) when the power supply is modulating the applied voltages with decades of MHz bandwidth. Another issue in ET is the interaction between the RFPA and its dynamic supply.

The output impedance of the supply and the impedance of the RFPA (at drain terminal) should be known, such that an efficient system can be designed.

1.1 Problem Definition

The goal is to design a printed circuit board (PCB) prototype (officially named the IVm Board) in order to measure the current into and the voltage at the RFPA drain terminal. The design methods presented and applied in this thesis aim to improve performance and accuracy of the prototype, where a key part is to utilize PathWave ADS to find optimal circuit parameters which satisfy the design criteria for bandwidth and power limitations. In addition to designing a working IVm Board prototype, a bias tee must be designed (and evaluated) in order to measure the IVm Board when applying DC bias voltages. Finally, the measurement setup itself must be specified in order maintain the integrity of the measurements, and thus also the accuracy of the IVm Board characterization.

1.2 Focus and Limitations

In order to produce a working prototype within the limitations given by time and complexity, only fundamental amplifier theory is applied to the design process. Topics such as offset voltages, bias currents etc. are considered to be advanced steps and therefore out of scope. The focus is mainly on the gain and the bandwidth of the current measurement circuit. The voltage measurement circuit is very simple and provides little new in this work, and thus has limited time in the spotlight. Only the drain configuration for the prototype is evaluated in this thesis, however, section 3.2.3 justifies the design option for both a drain and gate configuration.

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1.3 Report Structure

This thesis is is structured into seven chapters, where this is the introduction. Chapter 2 presents the theory and background. It covers the op-amp and the relevant op-amp circuits. S-parameters are introduced as these have a key role in the methodologies. Chapter 3 covers the design methodology of the IVm Board and the Bias Tee in detail, including the schematic capture, PCB design, and simulations. Chapter 4 presents the measurement methods. The measurement setup and calibration procedure is described for accurate measurements. The S-parameter measurement procedure is given as a step-by-step process. Oscilloscope measurements are also presented as an alternate method. Chapter 5 presents the results from the simulations and the measurements.

The plots are described. Chapter 6 covers the discussion of the design- and measurement methods and the results. Finally, chapter 7 presents the concluding elements from the discussion. It also presents future works. In addition to these chapters, appendices are also at the end of this thesis.

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2 Theory and Background

This chapter presents the relevant theory and background knowledge that support and motivate the design methodology, measurements and the results. The reader of this thesis work is assumed to have a fundamental understanding of analog electronics and signal processing, underlying op-amps, in-amps and filters. It is considered crucial for the integrity and quality of this thesis to understand thepro et contraof the op-amp in the design phase. Only the principles are adopted as necessary theory/knowledge in this thesis work, and limited by such. Suggested reading material to cover topics that are not investigated, but still highly relevant, are thoroughly presented in the famous worksThe Art of Electronics[1] andMicroelectronic Circuits, also known as "Sedra/Smith"

[2].

2.1 Operation Amplifier Basics

An op-amp is a differential amplifier with two inputs and one output. The ideal op-amp has infinite input impedance and zero output impedance, making them suitable for buffer amplification. The gain𝐴𝑣,ddepends on the op-amp configuration in figure 2.1 and is controlled through voltage division resistors at the negative terminal, known asnegative feedback. The differential gain𝐴𝑣,d

(also known as the closed-loop gain [1]) is given as

𝐴𝑣,d= 𝑉o

𝑉i

=

⎧⎪

⎪⎪

⎪

⎨⎪

⎪⎪

⎪⎩

−𝑅2

𝑅₁ inverting, 1 +𝑅₂

𝑅1

non-inverting,

(2.1)

R₁ R₂

V_i

V_o

(a)

R₁ R₂

V_i

V_o

(b)

Fig. 2.1.:The configuration for the inverting op-amp (a) and the non-inverting op-amp (b).

3

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2.1.1 Differential- and Common-mode

A voltage source can be written as the sum of a differential- and common-mode source [3]:

𝑉i= 𝑉i,d+ 𝑉i,cm = (𝑉2− 𝑉1) +𝑉2+ 𝑉1

2 . (2.2)

Although ideally the op-amp will amplify only the differential input signal𝑉_i,dand reject com- pletely the common-mode input signal𝑉i,cm, a physical amplifier will have an output voltage𝑉o

given by

𝑉_o = 𝐴_𝑣,d𝑉_i,d+ 𝐴_𝑣,cm𝑉_i,cm, (2.3) where𝐴_𝑣,dand𝐴_𝑣,cmare the respective differential- and common-mode gains [2]. The common- mode gain is usually described through the datasheet-provided measure common-mode rejection ratio (CMRR), defined as

CMRR = 20 log |

|𝐴^𝑣,d|

| |

|𝐴^𝑣,cm|

|

. (2.4)

It is of interest to keep the CMRR as high as possible. Thus, only the differential voltage is amplified and available on the output; equation (2.1) is still valid, even though there is a common- mode signal present on the op-amp inputs.

2.1.2 Gain, Bandwidth and Compensation

The op-amp gain starts to roll off at some frequency, i.e., the open-loop gain drops to unity gain due to internal limitations (see section 2.4). Negative feedback can becomepositive feedback, promoting instability and oscillations, if the accumulated phase shift reaches180° at a frequency at which the loop gain is≥ 1. Thus, acompensatedop-amp utilize dominant-pole compensation in which a deliberate pole is introduced in order to to bring the gain down to unity before the frequency of instability. This reduces bandwidth. However, in some cases the bandwidth can be increased though external compensation. A feedback capacitor will for some given values, as presented in figure 2.2, introducepole-zero compensation, usually provided by component datasheets [1] [4].

(a) (b)

Fig. 2.2.:Small signal frequency responses for different gains (a) and feedback capacitors (b). Adapted from [4].

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2.2 Difference Amplifier

A difference amplifier responds to the difference between the two signals applied at its input and ideally rejects signals that are common to the two inputs [2]. A difference amplifier configured with voltage division resistors on the non-inverting input is shown in figure 2.3. The total output voltage is the superposition of the inverting and non-inverting input voltage, times their respective gain given in equation (2.1):

𝑉_o= 𝑉₂ (

𝑅₄

𝑅₃+ 𝑅₄) (1 +𝑅₂

𝑅₁)− 𝑉₁𝑅₂

𝑅₁. (2.5)

By balancing the resistors such that

𝑅2

𝑅1

= 𝑅4

𝑅3

, (2.6)

equation (2.5) simplifies to

𝑉_o= 𝑅₂ 𝑅1

(𝑉₂− 𝑉₁) , (2.7)

revealing a pure difference operation due to the voltage division resistors 𝑅₃ and𝑅₄. From equation (2.7) follows the difference gain of

𝐴_𝑣,d≜ 𝑉_o 𝑉2− 𝑉1

= 𝑅₂ 𝑅1

. (2.8)

Any imbalance in the resistor condition (i.e.,𝑅2/𝑅1≠ 𝑅4/𝑅3) will deteriorate the difference gain and thereby introduce a common-mode gain; using low-tolerance resistors is key [1].

R₁

R₃

R₂

R₄ V₁

V_o V₂

Fig. 2.3.:Op-amp configured as a difference amplifier.

2.3 Instrumentation Amplifier

Instrumentation amplifiers (in-amps) are used to measure and amplify small differential signals under the presence of large common-mode signals [3]. The common in-amp, depicted in figure 2.4, has two stages, where the output stage is the difference amplifier in section 2.2. The input stage consists of two op-amps which buffer the difference amplifier inputs. It provides a high differential gain through the gain resistor𝑅gand thus suppresses common-mode output. The difference amplifier stage provides a single-ended output while removing any further common-mode signal

2.2 Difference Amplifier 5

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present [1], even at unity-gain configurations due to the difference operation. The complete in-amp differential gain is the product of the respective gains from each stage, and is given as

𝐴_𝑣,d=

(1 +2𝑅_f 𝑅g)

𝑅_dif,f 𝑅dif,s

. (2.9)

From equation (2.9) it comes clear that a small resistor value for 𝑅_g will vastly increase the differential gain. The op-amp gain expressions require in general that the active circuits only transfer signals in forward direction;𝑆12 = 0(see section 2.7.1). Hence the termunilateral gain.

Rdif,s

R_dif,s

Rdif,f

R_dif,f R_f

Rf

Rg

U1

U2

U3

V_i1

V_i2

V_o

Gain-buﬀer amplifiers Diﬀerence amplifier Fig. 2.4.:The in-amp with stages highlighted.

2.4 Physical op-amps

A physical op-amp differs from the ideal op-amp by being band-limited and having mismatches such as input offset voltage, bias current, slew rate and CMRR. The slew rate describes how fast the output signal can change, thus, a high slew rate is desired for high frequency amplifiers. The op-amp compensation capacitance limits the slew rate [1].

Two physical op-amps are the THS3001 in [5] and the THS4631 in [4], manufactured by Texas Instruments.

THS3001 is a high-speed (i.e., slew rate) CF op-amp. It is compensated for maximum bandwidth, which at unity-gain is420 MHz. Consistent with current feedback (CF) amplifiers, increasing the gain is best accomplished by changing the gain resistor𝑅₁, not the feedback resistor𝑅₂(in figure 2.1) [6]. This is because the bandwidth of the amplifier is dominated by the feedback resistor value and internal dominant-pole capacitor. Once a frequency response is found suitable to a particular application, the value of the gain resistor can be adjusted to increase or decrease the overall amplifier gain [5]. The THS3001 datasheet provides common feedback resistor values and corresponding bandwidths.

THS4631 is a high-speed field effect transistor (FET)-input op-amp with a high gain-bandwidth product (GBWP) of 210 MHz. In addition, it has low distortion- and noise characteristics as

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well as voltage offset errors, albeit being an FET-input amplifier [1]. This makes it suitable for measurement purposes where high signal-to-noise ratios (SNRs) are crucial. Its high CMRR makes it highly applicable for difference amplification purposes. The datasheet [4] provides feedback capacitor examples to compensate and ensure stable designs.

2.5 DC Gain Calculation

In a real design additional components are added to adopt to the real situation given by external conditions. An in-amp with a sensing resistor𝑅sensebetween the input terminals is depicted in figure 2.5. It has additional voltage division networks before each buffer inputs and an output matching resistor𝑅match. These resistors add loss to the total composite gain of the in-amp. To get a better grasp of the total composite gain, the in-amp is divided into four stages for gain analysis:

1. This stage consists of a source𝑅sourceand a load𝑅load, in series with the sensing resistor 𝑅_sense. The gain𝐺₁is the voltage division across𝑅_sense(i.e., across port 1 and 2).

2. This stage is the voltage division resistors between each port into the respective input buffer amplifier. The gain𝐺₂is the voltage division, considered twice as there are two buffer inputs.

3. This stage is the in-amp itself, where equation (2.9) provides the gain𝐺₃= 𝐴_𝑣,d. 4. This stage has a matching resistor𝑅matchfollowed by the port termination load𝑅load.

The gain𝐺₄is the voltage division ratio across𝑅_load.

The total DC gain𝐺totfor the in-amp is the product of the gain in every stage, however, notice that every gain, except the in-amp gain𝐺₃, is in fact resistive loss from voltage division. These can be gathered into a separate resistive gain factor

𝐺r ≜ 1

𝐿 = 𝐺1⋅ 𝐺2⋅ 𝐺4= (

𝑅_sense

𝑅sense+ 𝑅source+ 𝑅load) ( 2𝑅i,p

𝑅i,p+ 𝑅i,s) (

𝑅_match

𝑅match+ 𝑅load). (2.10) Combining equations (2.9) and (2.10) result in the simpler total gain expression of

𝐺tot= 𝐺r⋅ 𝐴𝑣,d. = 𝐺r(1 + 2𝑅f

𝑅g) 𝑅dif,f

𝑅dif,s

. (2.11)

2.5 DC Gain Calculation 7

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Rdif,s

R_dif,s

Rdif,f

R_dif,f R_f

Rf

R_g U1

U2

U3 V_i+

V_i–

Rmatch Vo,current

R_i,p Ri,s

Ri,p

Ri,s

R_sense R_source

Rload

Vin

Vout

Fig. 2.5.:The in-amp with source, load, sensing, voltage division and matching resistors.

2.6 Thermal Resistance

In [7], the thermal resistances𝜃^JAand𝜃^JCare introduced as metrics used for calculating thermal performance of plastic integrated circuit (IC) packages. Temperature resistance between the IC junction and the air is defined as

𝜃JA= 𝑇_J− 𝑇_A

𝑃 , (2.12)

where

𝑇_J: junction temperature of the IC, 𝑇_A: ambient temperature of the air,

𝑃: power to the IC.

Same approach applies to the temperature resistance 𝜃JC between the junction and the cas- ing.

T_A θ_JA

T_J T_C

θ_JC

Fig. 2.6.:IC package thermal metrics. Adapted from [7].

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2.7 Network Analysis

2.7.1 S-parameters

Scattering parameters, or S-parameters of linear electronic circuits are measured without the need of short-circuiting or open-circuiting input and output ports. The ports are instead terminated in fixed, known reference impedances. S-parameters of a linear two-port network interrelate incident and reflected waves of energy at input and output ports instead of voltages and currents [8], [9]. The reference impedance, famously referred to as the characteristic impedance is in most cases¹𝑍0 = 50 Ω. When a port is terminated with an arbitrary load𝑍L ≠ 𝑍0a traveling wave reflection is excited [10]. The reflection coefficient is defined as

Γ = 𝑉⁻

𝑉⁺ = 𝑍L− 𝑍0

𝑍_L+ 𝑍₀. (2.13)

Reducing the reflection toΓ = 0is done by letting𝑍L = 𝑍0, known as port matching. Extending this to a two-port network, the relationship between respective normalized incident waves and reflected waves

𝑎 = 𝑉⁺

√𝑍₀ (2.14)

and

𝑏 = 𝑉⁻

√𝑍₀ (2.15)

at port 1 and 2 is given by

[ 𝑏₁ 𝑏₂]=

[

𝑆₁₁ 𝑆₁₂ 𝑆₂₁ 𝑆₂₂] [

𝑎₁

𝑎₂], (2.16)

where the scattering matrix

𝐒 =[

𝑆11 𝑆12

𝑆21 𝑆22] (2.17)

contains the S-parameter elements for the two-port network. Remember, an S-parameter is a transfer function that describes the complex wave amplitude (magnitude and phase) ratios between ports. Going even further to the case of an 𝑛-port network where {𝑖, 𝑗} ∈ 𝑛, the S-parameter element between ports𝑖and𝑗 is defined as

𝑆𝑖𝑗 = 𝑉_𝑖⁻

𝑉_𝑗⁺, (2.18)

if and only if all other ports are set to zero. This implies no incident waves coming from other ports, thus, they must be terminated in matched loads to avoid reflections [10]. Equation (2.18) coincides with the one-port reflection coefficientΓin equation (2.13) when𝑖 = 𝑗 = 1.

S-parameters are complex in value and are frequency quantities [9], which make them very applicable when working across bands of frequencies, such as in amplifiers and filters. A two-port network is illustrated in figure 2.7, displaying the ports, waves and scattering nature. Take note of the position variable𝑥 on each port of the network. These mark thereference planes for the waves. Because traveling waves are spatially dependent, meaning the phase changes with position, the S-parameters are also spatially dependent. This is why a reference plane must be specified when working with S-parameters. When working with a device under test (DUT) at

1This is also the case in this thesis work.

2.7 Network Analysis 9

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Two-port network a1

b1

a2

b2

Port 1 Port 2

x₁ x₂

Z_c1 S₁₁ S₂₂ Z_c2

S21

S12

Fig. 2.7.:Two-port network and its scattering parameters illustrated.

lower frequencies, the wavelengths are much greater than the DUT itself and the phase is less spatially dependent [11]. Thus S-parameter errors are less crucial.

2.7.2 Errors in Measurements

Vector network analyzer (VNA) measurements are lossy and have errors embedded. Calibrating the VNA using the calibration method short-open-load-through (SOLT)²removes most of the systematic errors and averaging the measurements may reduce random errors [12]. From section 2.7.1, the definition of S-parameters in equation (2.18) require ports that are not excited to be terminated with reference loads. If the loads are not matched, reflected energy will propagate back to the ports which are measured [10].

2.7.3 Port Impedance

The complex reflection coefficient located at port𝑛,

Γ_𝑛 = |Γ_𝑛|

∠

^𝜃𝑛, (2.19)

can be used to calculate the impedance at this port [10]. A port terminated with the characteristic impedance𝑍₀= 50 Ωand with no reverse transmission (the case for output ports of unilateral amplifiers) has the complex impedance given by

𝑍𝑛 = 𝑍0

1 + Γ𝑛

1 − Γ_𝑛. (2.20)

2.8 Bias Tee Circuit

In circuit simulation, ideal DC or AC block components separate AC networks from DC networks.

In practical setups, this corresponds to isolating DC and AC sources from each other, mainly for circuit protection. A high DC into an AC source (e.g. a VNA used for S-parameter measurements) may destroy it. A second reason for isolation is to keep measurements correct. A leaking RF signal into a DC source may cause unwanted effects such as DC modulation from third-order intermodulation distortion, as well as reflections from the DC source’s unknown RF impedance [10]. In physical measurements isolation is realized with a bias tee – a passive three port device (see figure 2.8) with AC (P1) and DC (P3) input ports and an output port (P2). A high-pass filter

2Also known as through-open-short-match (TOSM).

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isolates AC or RF from the DC source, and is usually made up of DC blocking capacitors. A low-pass filter isolates the DC source from AC, however, as the low-pass filter requires large inductance and capacitance values, parasitics of the elements causing resonances in the RF band are non-negligible and the primary limitation for a wide bandwidth bias tee [13].

C L

P3

P2 P1

Fig. 2.8.:Simple bias tee circuit. P1 is the AC feed, P2 is the output port and P3 is the DC feed.

2.8 Bias Tee Circuit 11

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3 Design Methodology

This chapter describes the design methodology with necessary motivations. Allkey resultsare presented in chapter 5, whereas results that motivate the design (methodology) process itself are presented consecutively in this chapter. The physical measurement methodology in this work is presented in chapter 4.

3.1 IVm Board: Introduction

The design in this work is based on a predecessing prototype in figure 3.1, however, everything is redone from scratch and as such, is presented as a standalone prototype. The current and voltage measurement prototype is in this work named theIVm Board. The predecessing prototype is referred to as IVm Board v0.1.0, but is only reference in this introduction and therefore considered out of scope, hence predecessor. The designed prototype in this work is iterated up to IVm Board v0.2.0 and is simply just referred to asIVm Board.

Fig. 3.1.:Printed circuit board (PCB) of the predecessing prototype.

IVm Board v0.1.0 does not have a schematic capture, as its PCB was directly drawn in PathWave ADS layout. It has no simulation data and was therefore not tested by any means prior to physical measurements. The IVm Board v0.1.0 PCB prototype has big vias, does not have optimal component placement and lacks thorough signal integrity (SI) and power integrity (PI) implementations. A core design approach for IVm Board v0.2.0 is therefore to address these occurrences as well, during the design phase. In addition to a complete re-design, simulations are conducted in Advanced Design System (ADS) to further back up the required design criteria presented in table 3.1 (see figure 3.3 for the nomenclature).

13

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Tab. 3.1.:IVm Board Specifications

Design Criteria Description Value

𝑉_in Input voltage range 5 Vto30 V

Δ𝑉_max Max voltage drop between P1 and P2 < 0.1 V^†

𝑉P3,max Max out voltage for current meas. 3 V^†

𝑉P4,max Max out voltage for voltage meas. 2 V^†

𝐵_6dB Bandwidth > 200 MHz

𝑍out Output impedance on meas. ports 50 Ω

†At maximum input voltage and current of28 Vand0.5 A.

3.2 IVm Board: Design

The design process of IVm Board may present itself as a streamlined process, while in reality this is quite not the case. It is iterative, meaning circuit simulations and other key calculations are conductedin tandemwith the process of schematic capture and PCB design. A design reuse workflow is also strictly embraced with aim on reducing complexity, the bill of materials (BOM) and other potential pitfalls like footprint ambiguity. For instance, IVm Board is equipped with four op-amps in total, all having identical footprints and pin configurations. This reduces circuit complexity and allows for design reuse. The following sections present the PCB design and simulations of the IVm Board. Isometric drawings of the designed PCB of IVm Board v0.2.0 are presented in figure 3.2 and shows that components are mounted on both sides.

(a) (b)

Fig. 3.2.:Isometric view of IVm Board v0.2.0.

3.2.1 IVm Board Configuration

The IVm Board configured in its intended measurement setup is illustrated in figure 3.3. Normally, the envelope tracking (ET) source supplies the drain voltage to the RF power amplifier (RFPA), however, placing the IVm Board in-between separates this drain voltage into𝑉_inon the input port P1 and𝑉_outon the output port P2. Thus, the drain current to be measured will be the current through the sensing/measurement resistor(s), and is given by

𝐼_m = 𝑉_in− 𝑉_out 𝑅sense

. (3.1)

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The value of𝑅sense is found by evaluating the design criteria in section 3.2.4 and using equation (3.1). Since𝐼_max= 0.5 Aand

𝑉_in− 𝑉_out= Δ𝑉_max= 0.1 V, (3.2) the resistance is

𝑅_sense = 0.2 Ω (3.3)

and maximum power dissipation is

𝑃max= 50 mW. (3.4)

An important design choice lies in designing a correct reference plane for the measurements.

It is the RFPA drain impedance which is to be measured. To ensure a reference plane at the drain terminal, the voltage measurement circuit is fed the drain voltage from the RFPA itself, through theVREFpin on the PCB (see figure 3.3). In other words, not the output voltage𝑉out

from the sensing resistor𝑅senseinto the RFPA. This is because𝑉outmay have phase errors (for high frequencies) due to the physical trace length. The measured current is located across𝑅_sense and can likewise be assumed to have a different phase as it is not exactly at drain terminal.

RFPA Envelope

Tracker

P1

P2

P3

P4

V_o,current Vo,voltage

V_in

Vout Vref

Fig. 3.3.:IVm Board between the tracker source and the RFPA drain.

The output voltages from P3 and P4 should by design be proportional with the measured drain current𝐼macross𝑅senseand the reference drain voltage𝑉refat theVREFpin:

𝑉_o,current∝ 𝐼_m, (3.5)

𝑉_o,voltage ∝ 𝑉_ref. (3.6)

3.2.2 Op-amps and Circuit Configuration

IVm Board has sub-circuits for measuring the respective current and voltage from the tracker source. The current measurement sub-circuit is an in-amp built from three op-amps. The gain- buffer stage of the in-amp uses THS3001 op-amps, whereas the difference amplifier stage uses the THS4631 op-amp. The application of THS3001 is motivated by its wide operation bandwidth and THS4631 for its high common-mode rejection ratio (CMRR).

3.2 IVm Board: Design 15

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The voltage measurement sub-circuit is quite simple compared to the in-amp: it is a plain gain- buffer amplifier, also by the use of THS3001 op-amp due to its high bandwidth and slew rate. The IVm Board design process mainly concentrates on the in-amp, which is a far more complicated circuit than the very basic voltage buffer op-amp circuit.

3.2.3 Schematic Capture

The schematic capture (and PCB design) of IVm Board is in whole conducted in Altium Designer 20. For a more transparent design, the IVm Board is captured usingdesign variants, where one project contains resources for different configurations. This is motivated by the fact that a drain configuration will likely have variations in component values compared to a gate configuration.

Design variants thus enables both configurations to share the same PCB layout, in the same Altium Designer project. The schematic capture workflow covers the following, but is not limited to:

Component design (including footprints).

Component documentation.

Component integrity.

Power port and net labels.

Annotation of the schematics.

The amplifier sub-circuits (as described in section 3.2.2) are drawn separately, but arelogically connected using power ports. The output ports¹are equipped with series resistors of47 Ω(close value in the E24 series). Since the op-amps have very small output impedances ([4], [5]) the output resistance willroughly be approaching the design criterion impedance of𝑍_out = 50 Ω, in table 3.1 (results are presented in section 5.2.4). This is with aim to suppress reflections. A transmission line (TL) parameter is applied to the net between the output resistors and respective output connectors as design rule. This (SI) design rule is used to compute the TL parameters in the PCB design stage in section 3.2.4. The sensing resistor is designed to maintain both equations (3.3) and (3.4) found in section 3.1, thus𝑅senseis captured as several resistors in parallel as a precaution. The in-amp sub-circuit is depicted in figure 3.4 and showcases the component variations having green values, the logical connectivity using power ports and net labels and the design rule applied on the output. The voltage measurement sub-circuit consists of the THS3001 op-amp in non-inverting mode and with a gain of 2. The PCB prints (and all schematics) are also available appendix A.

Component Design

Altium Designer has an embedded component database providing access to components with parameters, footprints, models and supplier chains. This useful feature is though only partly used. Every component is manually designed and stored in local libraries inside the project file.

This is motivated by the IVm Board having a small BOM and simple components. The schematic components (or symbols) may contain several footprints, models or other necessary data. This allows for designing for headroom. Two examples are the SMA-connectors and the pin headers used in the design. The SMA-connector symbol has two different (but still similar) footprints, which can easily be switched between if there is e.g. a component shortage. The pin headers

1Note: On the IVm Board PCB the current measurement port is P4 and the voltage measurement port is P5. This differs from the port setup used throughout this thesis, as defined in figure 3.7 on page 20.

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6 3

2 U1A

THS3001ID

3 6 2 U4A

THS4631D R9

150R

R10 150R R15

680R

R17 680R R16 33R R6

10k R5

1k

R7

10k R8

1k

R11 560R R14 560R

R13 47R R1

0.8R i

Transmission Line VIN

VOUT

DIFF_OUT

6 3

2 U2A

THS3001ID

P4 R2 SMA

0.8R R3 0.8R R4

0.8R i

Rsense

V2+

V2- V1+

V1-

Vo- Rg = 2R

Av – 1 _____

R = 0.2Ω Vo+

Fig. 3.4.:Compiled schematic in Altium Designer for the in-amp.

have2.54 mmpitch (known as standard pitch) and are through hole (TH) for compatibility and flexibility. The importance of this is addressed later in section 3.2.4.

Component Documentation

Each component is affiliated with the most recent documentation. All symbols have embedded parameters and datasheets/assembly instructions. The parameters consist of e.g. component value, package reference or pin count to name a few. All components share the same parameter fields, as these are compiled into a BOM in the finished project documentation, applicable for component ordering or when mounting. In addition to parameters, corresponding datasheets (or other relevant component documentation) are attached as links. These are also accessible in the compiled resources (see appendix A).

Component Integrity

The iterative step in component design is the aspect of assessing the integrity, with iterative meaning going back and forth to find the best compromise in terms of restrictions like e.g.

maximum allowed current or bandwidth. Examples of key integrity situations in this project is that resistors must be able to handle the rated power this project requires, and that capacitors must bypass sufficiently across the specified voltage and frequency range. The smallest component size applicable is the relatively large 0603 package²as smaller packages have too low power ratings.

Since PCB real estate is not a limiting factor for the IVm Board, 0603 is not an issue sizewise.

The resistors have a low tolerance of1 %and a power rating of0.1 W. Tolerance simulation (addressing in-amp gain deviation) is conducted later on in section 3.3.4.

The capacitors used for bypassing are multi-layer ceramic capacitors (MLCCs) in 0603 and 1210 package sizes. They are manufactured by Murata and have high self resonant frequencies (SRFs) and low equivalent series resistances (ESRs), both being strongly dependent on the MLCC package size. Their resonance-behavior is shown in figure 3.5a. A high capacitance value is preferred to ensure good PI [5]. The 1206 capacitor with a capacitance of10.0µFensures this. However, its bandwidth is very low, as shown in figure 3.5a. Every op-amp power pin on the IVm Board has 0603 capacitors in parallel with 1206 capacitors to increase the resonance bandwidth. Since capacitors in parallel adds in value, the effective capacitance is still decided by the 1206 capacitor.

Both types have high voltage ratings to accommodate for the capacitance drop at higher DC

2In this project, imperial units are used to describe resistor and capacitor packages.

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voltages. This is very important to have in mind when selecting MLCCs. In figure 3.5b, the 1206 capacitor has a listed DC capacitance of10.0µF, but drops to2.00µFwhen biased with15.0 V DC³. Nevertheless, this capacitance is considered to be high enough.

10² 10⁴ 10⁶ 10⁸ 10¹⁰

Frequency [Hz]

10^-2 10⁰ 10² 10⁴

XC[]

0603 1206 0603 || 1206

(a)

0 5 10 15 20 25 30 35 40 45 50

DC Bias Voltage [V]

0 2 4 6 8 10 12

Capacitance [µF]

1206 0603 || 1206

(b)

Fig. 3.5.:The reactances vs. frequency (a) and capacitance vs. DC bias voltage (b) for the MLCCs. The capacitances evaluated in the plots are100 nFfor 0603 and10.0µFfor 1210. Plot data generated from SimSurfing.

3.2.4 PCB Design

The finished, fully mounted PCB of IVm Board v0.2.0 is shown in figure 3.6. The2 × 4pin headers are assembled on the top layer, as captured in Altium Designer. It turns out this is not compatible with the envelope tracker and the RFPA, also equipped with identical headers. The usage of standard pitch TH footprints for these connectors has actually solved the problem; the header can be swapped to a socket. In addition, the IVm Board should be mounted on top of these units, meaning the (now) sockets must be assembled on the bottom layer. Again, the implementation of TH components has solved this ambiguity.

The voltage buffer-amplifier lacks voltage division resistors prior to its input terminal. This is corrected on the physical PCB. The series resistor𝑅_i,sis mounted by scratching off solder mask and cutting the trace between theVREFpin and the op-amp. Since the PCB has ground planes, the shunt resistor𝑅i,pis also easily mountable, simply by scratching off solder mask.

The feedback capacitor𝐶_Fin the difference amplifier circuit is not captured in the schematics (see section 3.3.2 for the introduction of this). Luckily, as𝐶Fis a shunt component, it is mounted on top of the feedback resistor𝑅14on the PCB.

(a) (b)

Fig. 3.6.:Fully assembled PCB of IVm Board v0.2.0.

3Because MLCCs are unipolar, the same holds for−15.0 V.

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Signal Integrity and Power Integrity

The V_DDand V_SSrails are connected in star topology to reduce voltage drops from bus loading.

The exception is V_DDon U2, which shares V_DDtrace with U1 due to routing restrictions. This is, however, waived as they are in the same stage (the gain-buffer amplifiers in figure 2.4 on page 6). The bottom layer has a ground plane to allow for wider current return paths. However, cutouts are present beneath the op-amps themselves because a ground plane too close to the feedback network will add unwanted capacitance [5] and thus also an unwanted pole. Poles usually deteriorate bandwidths and should thus be limited by design. The amplifier output traces are TLs with impedance of𝑍₀= 50 Ω. The PCB has two layers with ground polygons on both sides, which is why the TLs are incorporated as grounded coplanar waveguides (GCPWs). An impedance profileis computed in Altium Designer and uses stackup parameters (among others) to automatically compute the GCPW. A precise stackup is not provided byPCBWay⁴for two-layer designs. Thus, typical parameter values for two-layer PCBs are applied to the Layer Stackup in Altium Designer:

𝜀𝑟 = 4.2, 𝑇FR−4= 1.6 mm, 𝑇_cond= 35µm.

The impedance profile is applied as a design rule for the GCPWs. This automates retracing if the Layer Stackup changes.

Thermal Characteristics and Power Dissipation

The op-amps come in small outline integrated circuit (SOIC) packages of the D0008A type. These do not have thermal pads for heat exchange with the PCB, so the power dissipation can only be controlled via the thermal resistance between the SOIC case and the air, either with heat sink or power limitation. The junction temperature of the op-amps are used to calculate the dissipated power allowed. The datasheets provide the required package dissipation ratings. For the D0008A package, the maximum junction temperature is 𝑇J,max = 125°C, and the thermal resistance towards the air is𝜃_JA = 97.5°C/W. The THS3001 datasheet has pre-calculated the power ratings for the two cases of ambient temperatures of𝑇_A ≤ 25°Cand𝑇_A = 85°C, but the maximum operating free-air temperature for the op-amp is70°C(commercial grade). Equation (2.12) is used to find the maximum power rating at𝑇_A = 70°C:

𝑃max= 𝑇J− 𝑇A

𝜃JA

= 125°C − 70.0°C

97.5°C/W = 564 mW.

This equals a relative change of−45 %compared to the power rating at ambient temperature 𝑇𝐴= 25°C. The maximum allowed current is then

𝐼_max= 𝑃_max

𝑉_DD− 𝑉_SS = 564 mW

30.0 V = 18.8 mA.

4PCBWayis the PCB manufacturer of use.

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If the ambient temperature is 𝑇𝐴 = 70°Cand the THS3001 op-amps draws more than 18 mA from the rails, an increased risk of distortion and other unwanted effects are predicted. For an industrial grade op-amp the current is even lower:

𝐼max= 410 mW

30.0 V = 13.7 mA.

The key is then to keep the ambient temperature at25°C, for instance by implementing passive/

active cooling through heat sinks/fans. Keeping the general circuit power dissipation low is also beneficial, which is addressed in section 3.3.1.

3.3 IVm Board: Simulations

Simulations of the IVm Board are done in PathWave ADS. Through simulations it is possible to assess different behavior in frequency responses and time-domain responses. Primarily, the frequency response of the in-amp is of interest, since the most crucial design goal is to achieve a wide band of operation and at the same time common-mode suppression. The goal of the simulation stage is to find optimal component values which satisfies the design criteria in table 3.1, which in turn is incorporated into the PCB design. See appendix B for the schematics and the simulation instances.

The simulation setup in all instances uses the default settings in ADS. The IVm Board is defined as a four-port network (see figure 3.7) for all simulations.

Rg

Current measure

Voltage measure I

V P2

P1

P3

P4

Fig. 3.7.:Four-port configuration of the IVm Board.

Texas Instruments provides P Spice models for both THS3001 and THS4631. The P Spice netlists are imported into ADS as components, for use in schematic capture and simulation. The IVm Board is then captured hierarchically throughcells. The current measurement circuit (i.e., the in-amp) is thus separated from the voltage measurement circuit into cells, acting as components higher up in the schematic hierarchy. This ensures easy design reuse for different simulation instances.

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3.3.1 DC Simulations

Voltage division resistors are applied before each input buffer to reduce the general power dissipation in the circuit and protect from clipping in the input buffer op-amps. The maximum allowed power dissipation per resistor of

𝑃max= 100 mW

is added to thewPmaxparameter in theResistor Device. This allows ADS to prompt whenever the dissipation is too high; a time-saving action for repeated simulations. Resistor values of

𝑅i,s= 10 kΩ, 𝑅i,p = 1.0 kΩ,

yield satisfyingly low power dissipation across the IVm Board circuit, at the cost of adding loss and thus lowering total amplifier gain.

3.3.2 S-parameter Simulations

Frequency response is assessed through S-parameter simulations, as these are complex and frequency quantities to begin with and thus very usable for amplifier analysis; amplifier magnitude- and phase can be directly evaluated. Assuming close to matched ports (i.e. the impedances are not way off ) and the fact that op-amps are unilateral, with the implication of

𝑆13= 0, 𝑆₁₄= 0,

the amplifier gain and phase for the in-amp and the buffer op-amp can be evaluated from the forward transmission coefficients𝑆31and𝑆41alone. A schematic for S-parameter simulations of the port configuration in figure 3.7 is captured, with all ports terminated with50 Ωport loads (as required by the S-parameter simulator instance). The simulator instance is configured to sweep over a frequency range of100 kHzto1.00 GHz,logarithmic, with a resolution of 100 data points per decade. This is beneficial as the frequency responses are generally plotted as bode plots. A logarithmic data set is also way more compact than a linear one in this case, because it spans over several decades. This simplifies further data processing in e.g. Matlab.

Amplifier theory in sections 2.3 to 2.5 are used to design the in-amp gain, in combination with the THS3001 and THS4631 datasheets. See figure 2.5 on page 8 for the component references.

The proposed resistor values for the in-amp after several simulation iterations are 𝑅_f= 680 Ω,

𝑅g= 33 Ω, 𝑅dif,f = 560 Ω, 𝑅dif,s= 150 Ω.

The gain resistor𝑅_gis very low compared to the feedback resistors in order to suppress common- mode input. The resulting value gives a sufficiently flat and broad bandwidth for the in-amp input buffer stage. The value of the feedback resistor𝑅fis provided by the THS3001 datasheet,

3.3 IVm Board: Simulations 21

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and is motivated by the compromise between bandwidth and stability. The difference amplifier resistors𝑅_dif,f and𝑅_dif,sare found through iterative simulations, where the design goal is set to match the previous stage’s gain level to achieve a flat frequency response (see figure 2.5 for the in-amp stages).

Feedback Capacitor

In the THS4631 datasheet a capacitor𝐶_Fis implemented in shunt with the feedback resistor and plots of typical characteristics across different capacitance values are given [4, p. 5]. The idea of implementing a feedback capacitor in the feedback network is thus proposed to increase the total in-amp bandwidth. This contradicts with the condition of balanced resistors in section 2.2 for the amplifier to maintain the correct difference gain. A capacitor in the feedback network looks at first glance like an integrator circuit with a band-limiting pole located at

𝑓c= 1 2𝜋 𝑅_dif,f𝐶F

.

This capacitor ambiguity is solved though simulation. A generic capacitor is added in parallel with the feedback resistor𝑅dif,f. By using theTuningfeature across the capacitance values from 1 pFto100 pF, the feedback capacitor value which provides the best result is

𝐶F= 33 pF.

The simulated frequency response, with and without𝐶F= 33 pF, is presented as a bode plot in figure 3.8. For the feedback capacitor response, the phase drops whereas the gain is lifted at some frequency when compared to the non-capacitor response, thus proving that a feedback capacitor of𝐶F = 33 pFincreases the bandwidth despite of the integrator ambiguity. This indicates a cancellation of a zero in the left half plane. The reason for this zero-cancellation is likely due to pole-zero compensation. While the THS4631 is a compensated op-amp, its datasheet suggests this technique is expected to be applied by the engineer, when looking at the suggested circuit examples and component values.

10⁵ 10⁶ 10⁷ 10⁸ 10⁹

Frequency [Hz]

-100 -80 -60 -40 -20

Gain [dB]

With capacitor No capacitor

(a)

10⁵ 10⁶ 10⁷ 10⁸ 10⁹

Frequency [Hz]

-180 -120 -60 0 60 120 180

Phase [ ° ]

With capacitor No capacitor

(b) Fig. 3.8.:Bode plot of the in-amp frequency response: gain (a) and phase (b).

Design of Measurement Board for Dynamic Impedance Measurements on Envelope Tracking Amplifiers

Eirik Hovde Skanke

Design of Measurement Board for Dynamic Impedance Measurements on Envelope Tracking Amplifiers

Master ’s thesis

Eirik Hovde Skanke

Design of Measurement Board for

Dynamic Impedance Measurements on Envelope Tracking Amplifiers

Abstract

Sammendrag

Acknowledgement

Contents

List of Figures

List of Tables

Glossary

Acronyms

1

Introduction

„

1.1 Problem Definition

1.2 Focus and Limitations

1.3 Report Structure

2

Theory and Background

2.1 Operation Amplifier Basics

2.1.1 Differential- and Common-mode

2.1.2 Gain, Bandwidth and Compensation

2.2 Difference Amplifier

2.3 Instrumentation Amplifier

2.4 Physical op-amps

2.5 DC Gain Calculation

2.6 Thermal Resistance

2.7 Network Analysis

2.7.1 S-parameters

2.7.2 Errors in Measurements

2.7.3 Port Impedance

∠

2.8 Bias Tee Circuit

3

Design Methodology

3.1 IVm Board: Introduction

3.2 IVm Board: Design

3.2.1 IVm Board Configuration

3.2.2 Op-amps and Circuit Configuration

3.2.3 Schematic Capture

3.2.4 PCB Design

3.3 IVm Board: Simulations

3.3.1 DC Simulations

3.3.2 S-parameter Simulations