Etching buried oxide at the bottom of high aspect ratio structures

As long as it is congregating the process is gregarious: however, when it passes the critical threshold of ipseity—that is, when it becomes a con- gregation—the process leads to

New IPROD DRIE tool give high quality electrode holes and fast etch times. However, reliability of IPROD tool not convincing with 3 long down periods

A deep reactive ion etching process was also developed to etch 14 μm round holes through 250 μm thick silicon wafer.. The first run is now fully completed and preliminary results

After the trenches were etched in the silicon device layer, a standard dielectric etch recipe (Recipe RF1) which uses RF substrate bias was used as a starting point for the

SEM image of DRIE holes resulted from a process in attempt to achieve 14µm round holes with an aspect ratio of 20:1 using an oxide mask.. Limited by the selectivity of oxide mask,

14 µm holes through 320 µm thick wafer bonded to support wafer in 40 min etch time. Etch stop against oxide with

Etch of the cavity housing the inertial sensor (a), Etch of the TSVs (b), oxidation of the wafer (c), fusion bonding of the capping wafer onto the device layer (d) and (e), Vias

Deep reactive ion etching (DRIE) is used to etch consecutively through the 40 µm silicon device layer, 2 µm buried oxide (BOX) and 300 µm silicon handle wafer.. In order to