TSV development for miniaturized MEMS acceleration switch

On this tool it is possible to run a switched etch process such as the BOSCH DRIE process as well as continuous etch processes such as dielectric etch or isotropic silicon etch,

After the trenches were etched in the silicon device layer, a standard dielectric etch recipe (Recipe RF1) which uses RF substrate bias was used as a starting point for the

The mechanical wafer consists of three layers, a 300 µm thick silicon substrate (yellow), a thin oxide layer (green) and a 35 µm thick silicon device layer (purple). The

The two key process technologies required for 3D integration are the fabrication of through silicon/substrate vias (TSVs) and chip-to-wafer or wafer-to-wafer bonding.. The

14 µm holes through 320 µm thick wafer bonded to support wafer in 40 min etch time. Etch stop against oxide with

9 shows a comparison of LET and LET MCA values in silicon for Fe ions of different energies in silicon calculated using SRIM, Geant4 and experiment using the 5 µm thin

Etch of the cavity housing the inertial sensor (a), Etch of the TSVs (b), oxidation of the wafer (c), fusion bonding of the capping wafer onto the device layer (d) and (e), Vias

Deep reactive ion etching (DRIE) is used to etch 7 x 70 µm trenches consecutively through the 40 µm silicon device layer, 2 µm buried oxide (BOX) and 300 µm silicon handle wafer.