Results of Enhanced Control Loops: Virtual Resistor

The power correction loop had the large drawback of requiring additional infrastructure invest-ments, and the Virtual Resistor (VR) was therefore proposed as an alternative, omitting the need for extra hardware installations altogether. The VR loop does however have the drawback of being far more difficult to implement into analytical models for use by methods, such as the quasi-steady approximate Lyapunov method, as the virtual resistor also changes the post-fault dynamics if the current is larger than I_set. While analytical modelling for the application of full-forward numerical integration is possible, this is kept outside of the scope of this thesis.

Before adding the Virtual Resistor (VR) to the system,Rvr must be chosen. For this thesisRvr

is set to

R_vr = 0.2p.u.= 0.0952 Ω (5.19) Furthermore, the current threshold activating the VR loop is set toI_set = 1p.u., and the Virtual Resistor is added to the grid side controller as depicted in Figure 5.2, with the actual Simulink implementation depicted in Appendix C.3, Figure C.11. The value ofR_vr was chosen without entering into detailed analysis maximising the potential of the control loop. Tuning the virtual resistor to the specific system could therefore improve upon the results found in this thesis. That being said, the idea behind the chosenR_vr = 0.2p.u. is that at the point where the amplitude of the current passesI_set = 1p.u. the imaginary active power consumed by the virtual resistor starts atP_Rvr = 0.2p.u. with an even higher virtual power being consumed for higher currents.

The system added with the virtual resistor was simulated using the same procedure as in Section 4.6.6 until the CCT was obtained. Simulation results yielded a critical clearing time of t_cc= 0.7606s, with a corresponding critical clearing angleδ_cc = 134.6213°. Dynamic responses for the system equipped with a VR when simulated for a clearing time equal to the CCT are provided in Figures 5.6 and 5.7, while the stability limits are summarised in Table 5.3.

Table 5.3: Results of stability analysis by simulating the system added with a VR in MAT-LAB/Simulink.

Parameter Value CCA,δ_cc 134.6213°

CCT,t_cc 0.7606s= 760.6ms

Lastly,I andM^stabfor the system added with a VR loop are calculated in (5.20a) and (5.20b), and further summarised for easy identification in Table 5.4.

I =

0.7606−0.3861 0.3861

·100% = 97.00% (5.20a)

M^stab =0.7606−0.3861 0.7606

·100% = 49.24% (5.20b)

The effect of the virtual resistor can be seen in Figure 5.6d, where the power injected by the converter as calculated by the control system,P_{V R,c}is far higher than the actual injected power P_{V R,act}. This will, as expected, reduce the power imbalance in the swing equation of the VSM,

Table 5.4: Quantified stability improvement for VR system.

Parameter Value

Stability limit improvement,I 97.00%

Stability margin,Mstab 49.24%

thus improving the angular stability. Furthermore, ∆P = P_{V R,c} −P_{V R,act} should equal the power consumed by the virtual resistor. UsingR_vr = 0.2, the current amplitude found in Figure 5.6f andP =RI², this is found to be as expected. In addition, as explained in Section 5.2.2, the added VR loop will not affect the reactive power injection of the VSM. This theory is confirmed looking at Figure 5.6d whereQ_{V R,act} and theQ_{V R,c}are identical.

The obtained stability limits summarised in Table 5.3 look very promising, with the CCT moved all the way up to760.6ms at a CCA of134.6213°. Furthermore, the stability limit improvement, I, and the stability margin,Mstab, of97.00%and 49.24%respectively are indeed very good.

This testifies towards what seems like an extreme improvement of the system stability using nothing else than an additional, digitally implemented control loop, and it is therefore beyond doubt that the VR loop achieves objective number one of improving the system stability.

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(b) Speed deviation∆ωof the VSM from the nominal grid frequency.

(d) Active power injectionP as calculated by the inverter and actual injection.

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(e) Reactive power injectionQas calculated by the inverter and actual injection.

Figure 5.6: Grid side response for control system equipped with virtual resistor fort_c=t_{cc,V R} = 0.7606s.

However, looking more closely at the system response in Figure 5.6 when pushed all the way to this high CCT, some major issues can be identified. The first indication of an undesirable system response can be seen already in Figure 5.6a where several seconds are needed for the power angle to return to the s.e.p.. Also, the characteristic of the rotor angle response is practically identical to the rotor angle response of the original system, an observation which also holds for the speed deviation in Figure 5.6b. Figure 5.6b does however reveal small oscillations in the frequency at the point where the VR loop is disabled.

The extremely low voltages seen in Figure 5.6c can be explained by recalling how the virtual resistor actually affects the system behaviour, namely by subtracting the voltage drop acrossRvr

from the control signale. Furthermore, the fact that the voltages are so low, and the relatively large voltage difference betweenEandV_pcc indicates that the converter current most likely is excessively high also for this enhanced control system, which is confirmed looking at Figure 5.6f. It should also be mentioned that voltages as low as0.4p.u. are unfeasible even on its own, as converters typically have a rated operating range also for voltages.

The virtual resistor loop almost doubles the critical clearing time of the system, but in addition to not solving the problem with the post-fault current, the VR brings a new issue that can be observed in Figure 5.6d. During fault, the desired operation is achieved, effectively decreasing the power imbalance and improving the stability. However, after the fault is cleared the virtual resistor is still active due to the high current, resulting in the control system acting as it follows the power set-point without actually injecting the desired power. It takes as much as 4 seconds after the fault is cleared for the VSM to again deliver the desired active power. It can therefore be concluded that not only is the post-fault current slightly higher than for the original system, but the current is high without the system delivering the desired power.

When it comes to the rotor side response in Figure 5.7, the large drop seen in the DC link voltage for the original system at the time of fault-clearing is not present in Figure 5.7a. This can be seen in connection to the low active power in Figure 5.7b, which also reaffirms the low actual power injection observed in Figure 5.6d. The mechanical speed in Figure 5.7c is higher for a longer period, as expected, due to the low electromagnetic torque applied to the PMSG after fault-clearing. This also affects the turbine itself, which due to having a higher mechanical speed

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(b) Powers calculated by the rectifier control system.

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(c) Mechanical rotor speed of the wind turbine.

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Power Coefficient of the Wind Turbine Cp

(d) Power coefficient of the wind turbine.

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(e) Mechanical torque of the wind turbine.

Figure 5.7: Rotor side response for control system equipped with virtual resistor for t_c = t_{cc,V R} = 0.7606s.

operates lower on the torque curve, and thus outputs a lower mechanical torque as seen in Figure 5.7e. Operating on the far right-hand side of the power/torque curves also implies a low power coefficient as seen in Figure 5.7d. However, as for the original system, the rotor side responses do not seem to affect the transient stability of the grid side, and the rectifier controller is able to achieve its controller objectives. The rotor side response is therefore concluded to be adequately

good.

To summarise, the system response when cleared at the CCT is to a large extent identical to what was seen for the original system, only with a longer clearing time and worsened active power injection post fault. The VR loop does however provide a better stability margin than the PCL, while still not solving the issue of the high post-fault current. As such, the first objective is achieved but not the second. It can be mentioned that the system added with the VR was also simulated for atc =tcc,P CL= 0.6444s, for which the results are depicted in Figures 5.11 and 5.12 in Section 5.3.4. The VR loop will hence be compared to the other enhanced control loops for that lower clearing time in Section 5.3.4.

5.3.3 Results of Enhanced Control Loops: Virtual Resistor and Damper