the PIXCNFG REGSEL and PIXCNFG DATA to the regions is skewed in the same fashion.
These skewed updates of the peripheral registers reflect in the driving of the select wires to column and rows and of the global data signal.
The usage of the skewing functionality together with advanced addressing features needs caution. It might lead to unexpected results if the user does not ensure that the column or row selection lines are all de-asserted in-between transactions, so that all pixel latches are disabled. For example the PIXCNFG REGSEL and PIXCNFG DATA are contained within one register and thus can be modified with a single control transaction. Flipping both bits in conjunction with skewing and without de-asserting all column and row select wires beforehand can lead to unexpected Mask and Pulse Enable patterns.
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Printed by SimVision from Cadence Design Systems, Inc.
Printed on Wed Jul 29 03:39:33 PM CEST 2015
PULSE to DPULSE Propagation Delay
Cursor-Baseline = -601.54ns Baseline = 92,242.18ns
Cursor = 91,640.64ns
PAD_DCTRL_I_P ITS_STROBE CMD_PULSE DPULSE CLK
0 0 0 0 0
Marker 2 = 92,067.46nsMarker 1 = 92,117.38ns
91,500ns 91,600ns 91,700ns 91,800ns 91,900ns 92,000ns 92,100ns 92,200ns 92,300ns
Baseline = 92,242.18ns TimeA = 91,640.64ns
Figure 3.18: Delay between the assertion of the first bit of the PULSE command and the assertion of the DPULSE as seen by the Matrix.
3.7.2 Automatic assertion of an internally generated STROBE following a PULSE command
It is possible to configure the circuit to generate automatically an internal TRIGGER com-mand following a PULSE comcom-mand (be it a DPULSE or an APULSE). This functionality is enabled via the setting of theEnable Test STROBE bit in the FROMU Configuration Register 1 (0x0004).
The delay between thepositive edgeof the internal PULSE signal and the assertion of the au-tomatically generated trigger is controlled via theFROMU Pulsing Register 1 (0x0007).
The value of the register incremented by one gives the delay in units of clock cycles. The duration of the assertion of the STROBE signal is still controllable with theFROMU Con-figuration Register 2 (0x0005).
3.7.3 Fan-out of pulse signals to the Matrix
The fan-out of the DPULSE/APULSE signals to the double columns is implemented in the region modules logic as illustrated in Fig. 3.19. Each region drives the DPULSE and APULSE inputs of 16 double columns, propagating the DPULSE or APULSE signals generated by the FROMU following a Pulse command.
A 16 bit Pulse Gating register (Fig. 3.19 and Fig. 3.15) controls the propagation of the DPULSE or APULSE signals to each double column. The propagation of a DPULSE or APULSE to a double column is enabled if the corresponding bit of the Pulse Gating register is set. The control of the fan-out of the APULSE/DPULSE signals aims at minimizing the current pulses needed to charge and discharge the large capacitance of the global APULSE and DPULSE nets, resulting from the sum of wiring capacitance and total gate-capacitance at the inputs of the pixels.
Additionally, the Pulse Gating registers are connected in a shift-and-rotate topology. The pulse gating pattern stored in the Pulse Gating registers can automatically shift and rotate after the de-assertion of the APULSE/DPULSE signal received from the FROMU. This func-tionality is optionally enabled using the Enable Rotate Pulse Lines bit of FROMU Con-figuration Register 1 (0x0004). The automatic rotation of the pulse gating pattern is intended to facilitate testing by reducing the number of control transactions needed to change the set of pixels that get pulsed.
The Pulse Gating registers are chained in two groups (region 0 to 15 and regions 16 to 31).
The shift output of the register in regionnconnects to the shift input of the register in region n+ 1. The shift output of the 16-th register of the group is connected back to the shift input of the first register of the group. Thus, the full set of 512 bits of the Pulse Gating registers are combined into two shift and rotate registers of 256 bits. This is illustrated in Figure 3.20.
The shift is triggered on the de-assertion of the DPULSE/APULSE input.
The content of the Pulse Gating registers can be read back through the scheme described in Section 3.6. The content of the registers after the automatic shift and rotate can therefore be directly inspected and the pulsing pattern always retrieved.
DPULSE[0] APULSE[0] DPULSE[1] APULSE[1] DPULSE[15] APULSE[15]
PULSE GATING SHIFT R/W REGISTER
SHIFT_IN SHIFT_OUT
SHIFT
from prev region to next region
CONTROL READ WRITE PULSE_REG_SHIFT
PULSE_REG_SHIFT is a single cycle pulse generated globally, on detection of the trailing edge of either the APULSE_FROMU of DPULSE_FROMU signals DPULSE_TO_REGION[n]
APULSE_TO_REGION[n]
Region level Pulse fanout module
Figure 3.19: Fan-out of the Pulsing signals to the Double Columns. Schematic diagram of the circuits in one of the region modules in the periphery, forwarding APULSE and DPULSE to 16 double columns.
Region 16 Region 17 Region 31
Region 0 Region 1 Region 15
SHIFT IN SHIFT
SHIFT OUT PULSE GATING
REGISTER
D Q D Q D Q D Q
SHIFT IN SHIFT OUT
bit 0 bit 1 bit 2 bit 15
SHIFT IN SHIFT
SHIFT OUT PULSE GATING
REGISTER
SHIFT IN SHIFT
SHIFT OUT PULSE GATING
REGISTER
SHIFT IN SHIFT
SHIFT OUT PULSE GATING
REGISTER
SHIFT IN SHIFT
SHIFT OUT PULSE GATING
REGISTER
SHIFT IN SHIFT
SHIFT OUT PULSE GATING
REGISTER
PULSE REG SHIFT
Figure 3.20: Pulse shift registers scheme where the rotation is triggered on the negative edge of a Test Pulse