UNIVERSITY OF OSLO Department of Informatics
Non-feedback
∆-∑ D/A converter system
Lars A. Fleischer
Cand Scient Thesis
7th February 2002
Acknowledgements
I would like to thank my supervisors Dag Trygve Wisland og Mats E. Høvin
for making this thesis possible.
Contents
1 Introduction 5
1.0.1 Organization of this thesis . . . 6
1.1 Background essay written as an introduction to oversampling ∆−Σdata conversion. . . 6
1.1.1 Oversampling technology in the article "Interpolaive digital to analog converters" by Ritchie, Candy and Ninke. . . 7
1.1.2 The second article "Oversampling Methods for A/D and D/A Conversion" by Candy and Temes. . . 9
2 The new pipelined ∆−Σ DA converter system 13 2.1 Interpolator . . . 14
2.1.1 First stage . . . 15
2.1.2 Linear interpolator - SINC . . . 16
2.2 Modulator - The new pipelined ∆−ΣDA converter . . . 22
2.2.1 Scaleable in order . . . 22
2.2.2 Pipelined . . . 23
2.2.3 Accumulator word length . . . 23
2.2.4 Pattern noise . . . 23
2.2.5 Mathematical equivalent . . . 24
2.3 Zeropadding . . . 27
3 Component, system and hardware simulating 29 3.1 Simulation of the pipelined ∆−ΣDA modulator . . . 29
3.2 DC sweep simulation - Pattern noise . . . 32
3.3 Amplitude scan . . . 32
3.4 Simulation of the sinc3 filter . . . 33
3.5 Simulation of the complete system . . . 35
3.6 The complete system implemented in VHDL . . . 36
3.6.1 The VHDL code . . . 37
3.6.2 The VHDL test bench . . . 38
4 Measured results 40
4.1 Components . . . 40
4.1.1 PC . . . 40
4.1.2 Altera - interpolator and DAC . . . 42
4.1.3 HCMOS Switch . . . 42
4.1.4 Analogue Low pass filter . . . 42
4.1.5 Crystal 120dB audio ADC . . . 43
4.1.6 Altera - Serial to parallel sequencer . . . 43
4.1.7 Sun workstation . . . 43
4.2 The VHDL code . . . 43
4.2.1 Word length . . . 44
4.3 Measured results . . . 44
4.4 Power supply . . . 47
5 Conclusion and future work 49 5.1 Summary . . . 49
5.2 Conclusion . . . 50
5.3 Future work . . . 51
5.3.1 Band pass filter . . . 51
6 Publication 52 6.1 Submitted to ICECS 2002 . . . 52
A Definitions 59 A.1 The Blackman-Harris-Hoodie window(bhh) . . . 59
A.2 The Blackman window . . . 59
B The simulation code for the new pipelined∆−Σ modulator 60 C DC sweep simulation 64 D Amplitude sweep simulation 69 E Sinc3 simulation 74 F The complete system simulation 77 G Additional VHDL code used in the simulation 81 H VHDL code implemented on the Altera chip 86 H.1 VHDL file "PLDS_DAC.VHD" . . . 86
H.2 VHDL file "CLKDIV.VHD" . . . 91
H.3 VHDL file "SER2PAR.VHD" . . . 93
H.4 VHDL file "DIFF.VHD" . . . 95
H.5 VHDL file "AKKUM.VHD" . . . 96
H.6 VHDL file "AKKUM3.VHD" . . . 97 H.7 VHDL file "differens.vhd" . . . 98 H.8 VHDL file "zeropadder.vhd" . . . 99
Chapter 1
Introduction
To understand the fundamental of data conversion it is necessary to see it as the transformation from one domain to the other. The conversion is from the digital to the analogue domain. While the analogue domain has an unlimited numbers of levels the digital has only a limited number. In a similar way has the analogue domain an unlimited numbers of samples per second while the digital is limited.
Conventional D/A1 converters often use a network of switches and resis- tors to generate an analog output signal. In decoding N-bit binary words the switched network must normally contain N switches and the resistor net- work must have a precision to gain2N different output levels. With a large N-bit word, typical greater than ten, the resistor networks are difficult and expensive to make. The resolution of conventional digital-to-analog convert- ers is limited by the accuracy of the components in the analog part of the converter.
A way to avoid many of the difficulties encountered with conventional methods in D/A converters is to use a well-established technique called delta-sigma noise shaping [1]. This technique will increase the resolution, however it will lead to increased complexity and thereby increased power consumption. The complexity of the global feedback loops might limit the clock speed of these converters.
In [2] a new technique for∆−ΣA/D modulation is described. It describes a modulator with no global feedback loops and this method can be used in D/A conversion with some modifications. The emphases for this thesis is to design, simulate, implement and measure the new pipelined first order∆−Σ digital to analogue modulator. Since this new modulator is mathematical equivalent with the conventional one there are no differences when simulating them. The difference is the higher oversampling ratios for the new pipelined modulator when the system is implemented. This difference is more evident when the modulator has a higher order.
1Digital to analogue
1.0.1 Organization of this thesis
This thesis starts with a discussion over two articles central in the area of traditional methods oversampling data conversion. This discussion has been written as an essay in relation with the introduction course for new students starting with its thesis. It is meant to be a start on the report produced during the main subject, and as training on producing a large scientific paper. The first one by Ritchie, Candy and Ninke was published November 1974 and describes the theory behind oversampling data conversion. The second article deals with oversampling data conversion and the interpolation problem. It shows techniques for interpolating that is increasing the sampling rate and removing unwanted frequency components.
Chapter two describes the new pipelined first order ∆−Σ modulator and its mathematical equivalence to the traditional∆−Σmodulator. This is part of the measurement system together with the interpolation stage, which includes both a FIR and a sinc filter.
The simulations in chapter three include simulations of the pipelined modulator, the interpolating sinc filter, the converter system and the VHDL implementation. It is performed a pattern noise simulation of the modulator with different oversampling ratios, and an in band noise simulation with different amplitude levels.
The goal for this thesis was to make a working D/A system with the new pipelined modulator. In chapter four the different parts of the converter system is described together with the measurement system. The VHDL implementation, which was simulated in the previous chapter, is here used in the D/A system.
Results and future work are discussed after that in chapter five. The important aspect of the new modulator of higher order is the possibility of a higher clock rate then the old modulator of equal order.
Results and work from this paper have been used in a submitted paper to ICECS 2002, from Departments of Informatics, University of Oslo. This paper is shown in chapter six.
The appendixes show simulation code and the VHDL code used in the simulation and implementation.
1.1 Background essay written as an introduction to oversampling ∆ − Σ data conversion.
This essay has been written in relation with the introduction course for new students starting with its thesis. This essay is based on articles that deal with oversampling methods for digital to analogue conversion. The first article
"Interpolaive digital to analog converters" [5]
1.1.1 Oversampling technology in the article "Interpolaive digital to analog converters" by Ritchie, Candy and Ninke.
This thesis describes a new technique for converting digital signals to ana- log form by using higher output frequency then the input signals sampling frequency, and coarser amplitude resolution then the N-bit word. There is a trade-off between speed and precision of operation where the precision in- creases with the speed. This trade-off is more suited for implementation in integrated circuit.
To understand the fundamentals of the proposed technique, the article
"Interpolative digital to analog converters" by G. R. Ritchie, James C. Candy and William H. Ninke, illustrates how to divide a N-bit word into aM+1-bit word with a frequency of fs∗2LHz [5]. To understand, consider the input N-bit data word supplied at period T to be composed into two sub words where the M-bit word consists of the most significant bits and the L-bit word consists of the least significant bits. Let the values of these words be denoted as m and lrespectively. The M-bit word will then be applied to a conventional D/A converter to provide(2M+ 1)output levels, and theL-bit word will be used to modulate the output levels to provide effectively fine resolution between these levels. When the L-bit word is used to modulate D/A output levels it must be filtered through a analog low pass filter with cutoff frequency1/2T. The representation nof a particular input word will be, as illustrated in figure 1.1, between themth and them+1th of the2M+1 available levels. We can express the desired output value nas
n=l+m2L (1.1)
And since mis only the value of the most significant bits we must multiply it with2L. This equation can also be written as
n=l(m+ 1) + (2L−l)m (1.2) If the same sample periodT is divided into2L subintervals and the output level is set equal to m for 2L −l subintervals and equal to m + 1 for l subintervals, as shown in figure 1.1, then the average output will be exactly the same as the desired output.
This can also be deduced from equation 1.2. Converters of this type are referred to as interpolative D/A converters because this procedure of averaging between coarse levels is related to simple linear interpolation. It is also important to emphasize that even an interpolative D/A will generate exactly the desired average output, there is a significant mean-square error.
For white noise the mean-square error will be given by E2= 1
22L
2L
X
l=1
[(2L−l)l2+l(2L−l)2] = 22L−1
6 (1.3)
output levels2M
Desired output
Interpolative D/A signals
2L timing subintervals m+1
m
n
Figure 1.1: Illustration of interpolation by time averaging,L= 4.
where the spacing of the2N levels are taken to be unity. The article "Inter- polative Digital-to-Analog Converters" presents three different implementa- tions of the interpolative D/A technique. Each technique will be different with regards to simplicity in implementation and performance measured in baseband distortion. The first implementation used a modulo-K accumula- tor, the second a binary rate multiplier, and the third a form of pulse-width modulation. These circuits are in this paper compared with respect to circuit complexity, sensitivity to circuit imperfection and the amount of baseband distortion introduced.
To get a better view of this technique let the M-bit word represent a coarse division of the function area and the L-bit word will represent the
PCM
Modulator Register
Nyquist clock
Digital filter
High speed clock
Analog output
Figure 1.2: The demodulation occurs at a sufficiently high sampling rate that digital filters can provide most of the antialiasing and smoothing functions.
levels in between. Since it’s output was theM-bit word, theL-bit word will represent the error in the output signal. The output signal in this figure will oscillate in a way as illustrated in figure 1.1.
1.1.2 The second article "Oversampling Methods for A/D and D/A Conversion" by Candy and Temes.
In an interpolative D/A converter the interpolation or up sampling func- tion is an important part of it. The basic discrete-time signal processing understanding is needed to understand why this is important. First the discrete-time signal is sampled which means it is limited in frequency from 0 tofs/2where fs is the sampling frequency[3]. Adding zeros between each sample increases the sampling frequency, but this also makes the frequency specter repeated higher in frequency in-between 0 and fs. These higher fre- quencies are unwanted and must be removed with a filter. The filtering part is one of the difficult parts of oversampling D/A conversion.
The article "Oversampling Methods for A/D and D/A Conversion" [6]
by J. C. Candy and G. C. Temes attempts to evaluate and compare the different techniques to show when they can be useful. It also shows methods of how to increase a signals sampling frequency.
And several mathematical methods for determining the performance of oversampling converters are presented. A number of important choices, tradeoffs and the effect of having non-ideal components, in the implementa- tion of converters, are discussed. In the end, several designs for D/A convert- ers are discussed. This article uses the figure 1.2 to explain the fundamental of oversampling D/A conversion [7]. In this figure a digital filter was used to interpolate sample values of the input in order to raise the word rate to a frequency well above the Nyquist rate [8]. Then a modulator truncates the word and converts the signal to analog form at the high sample rate. An example is used to illustrate the details of the oversampling technique for D/A conversion. By processing 4-kHz signal encoded into 16-bit words at 8kHz. Figure 1.4 shows what kind of parts the converter consists of, and figure 1.3 shows the spectra of the signals and the frequency response of the filters used. The input words are placed in a register from which they are fed into the low-pass filter. Since the low-pass filter is clocked at 32kHz, the output signal will resemble the PCM encoding of the signal at 32kHz.
The next stage is the linear interpolation that copies each word three times, raising the rate to 128kHz. In the modulator each word are repeated eight times, raising the rate to 1MHz, and then the code are rounded off to 1-bit words with a feedback quantizer. Then it is converted into analog form and smoothened with an analog low pass filter. When the word rate is sufficiently high, the quantization noise introduced into the signal is small or pushed into the higher frequencies, and the requirements of the analog filter are simple.
0 8 16 24 40 0 32 64 96 128 160 (d)
(c) (b) (a)
(i) (h) (g) (f) (e)
32
Figure 1.3: Spectra of signals and frequency response of filters used for interpolating sample values. (a) the baseband signal; (b) the specter of the sampled signal; (c) the frequency response of the low-pass filter included that of the holding register; (d) & (e) the output specter, drawn on different scales;
(f) the sinc2-shaped frequency response of linear interpolation; (g) the result of the interpolation; (h) the frequency response of the last register, which holds the signal between 128-kHz sample times; (i) the specter of the held signal.
Linear Interpolation 8kHz
8k word/s PCM
Register
32kHz 128kHz 1MHz
Low-pass filter
Analog output Modulator
Figure 1.4: This figure shows one design example when using oversampling converter.
x
MSBs LSBs
y x+e i-1-e i D/A
-ei Delay
-ei-1
Figure 1.5: This first order modulator is a digital quantization with error feedback
*2 Delay
Delay fs 4 fs
fs
Delay
18bit 16bit
2bit 2bit
Carry y First stage Second stage 16bit
x
- +
Figure 1.6: This second-order modulator has error feedback digital quantizer with auxiliary first-order quantization to 1-bit code.
The modulator stage
Figure 1.5 shows a implementation of a digital quantization with feedback [5]
The sum generated by the adder is quantized by using only its most signifi- cant bits as the output, and the least significant bits are delayed and added to the next input sample for error correction. This feedback loop will gen- erate an oscillating output signal, and the input value will indicate how fast the frequency will oscillate. It is also emphasized here that there are mean square error in the signal. For this and other reasons first-order demodula- tion is not widely used in application today, but was useful at times when it was important to have only very simple circuits in the modulator.
Higher-order noise shaping can be achieved by replacing the delay in the feedback loop by a predictor filter [10]. Figure 1.6 shows such a system and the first stage for the circuit is a digital quantizer with a second-order noise shaping. The second stage of the circuit is included to perform a first-order quantization of the 2-bit words to 1-bit ones [11]. One can avoid the need for the second stage by clocking the first one at a rate high enough. Figure 1.6 shows a modulator circuit which is cascaded to reduce its error noise.
Two first-order quantizers are cascaded where the derivative of the second- stage output signal is added to the output of the first-stage. The net output contains 2-bit words and this advantage allows the net output to oscillate between four levels, and this will avoid introducing excessive noise into larger signals. This advantage is outweighed by the need for high precision in the four-level D/A circuits required.
Figure 1.7 gives a example on implementation of a second-order quan-
Delay
Clip *2
Delay
+
E Quantizer
Y 1bit 16bit
X
18bit
1bit
19bit
18bit -
+
Figure 1.7: Equivalent circuit of a second-order digital delta-sigma quantizer.
tizer. The randomness in the oscillation pattern of second-order modulators depends on avoiding signals that are rational multiples of∆ in the integra- tors. Something that normally is impossible in digital implementation, where the signal values are always rational. One way of ensuring randomness is to inject a relatively large dither signal. Another way is to add a random bit pattern to the least significant bit of the input to mimic the effect of having irrational values stored in the first accumulator.
The first article describes the basic quantization technique thorough, and it gives you a view of the error it produces. Ones you understand the quanti- zation technique, you also understand how powerful it was and how it must have changed the digital to analog conversion. The increasing speed of up- coming integrated circuits will provide bigger possibilities for delta-sigma modulators. In theory, increased sampling rates can in crease the amplitude resolution indefinitely, but the resolution will always be limited by the noise of the circuits’ elements. The last article uses the example where conversion of 3.5MHz video signal requires modulation rates in excess of 100MHz.
Chapter 2
The new pipelined ∆ − Σ DA converter system
While the last chapter explained the conventional ∆−Σ DA modulator, does this chapter explain the new pipelined ∆−Σ DA converter. This new modulator has no global feedback loops and can be designed in a pipelined way. This design will make the modulator to run at a higher clock rate then the traditional one.
This chapter also describes the different parts of the converter system.
An important part of the∆−Σdata converter is the principles of sampling rate conversion. That is because the converter needs a signal with a higher sampling rate, which will reduce the mean-square error noise of the converter.
One efficient way to interpolate or sample up the signal is in two stages.
The first stage is a low-pass filter which is implemented in a multistage solution with a finite impulse response (FIR) filter [6] as its first stage. The second stage is a linear interpolator implemented as a sincK shaped filter function. Figure 2.1 shows the block diagram of the system(converter). The signal enters as pulse code modulated (PCM) signal with a sampling fre- quency of 1kHz.
Linear Interpolation 8kHz
8k word/s PCM
Register
32kHz 128kHz 1MHz
Low-pass filter
Analog output Modulator
Figure 2.1: This figure shows a converter design with multistage low pass filter.
w(m) F’=LF
L h(m) y(m)
F’
x(n) F
Figure 2.2: Block diagram over an interpolator which interpolates by a factor L
2.1 Interpolator
The design of an interpolator basically revolves around the design of a digital low-pass filter. Any number of classical filter designs could in principle be applied to meet these requirements. But many of these classical techniques are often ruled out because of the multirate and multistage considerations.
Designs that can take better advantage of the above criteria and achieve a more efficient design are often driven by practical hardware considerations, in particular when extremely high sampling rates are used. The specifications of the application determine the choice of the architecture. For example, most digital audio converters require a strict linear phase. And since IIR filters does not have a linear phase it is ruled out as an intermediate-stage decimator.
Interpolating a signal by an integer factor L is shown by the block dia- gram in figure 2.2. The input signalx(n)with a sampling frequency F, will increase its sampling frequency by inserting L−1 zero-valued samples be- tween each sample ofx(n). w(m)is the intermediate signal with a sampling frequencyLF, and it contains the desired baseband information ofx(n), but it also hasL−1imaged replications of this specter at frequencies aboveπ/L that are undesired. Figure 2.3 illustrates time- and spectral-domain inter- pretation for these signals for the case when L = 3. A low-pass filter will remove these undesired images, and in the time domain it will effectively interpolate the zero-valued samples to their desired values.
The technique of inserting zero-valued samples between each sample to increase the sampling frequency can also be achieved by repeating a sample in a sample-and-hold technique. This will increase the signals power because the sum of each sample value in the signal is bigger then summation of the original signal. With the first technique the power will be the same since no extra sample values is added only zero-valued samples. Because of this the sample-and-hold technique is not preferred.
The input-to-output relation for this interpolation process can be shown [9] to be
y(m) = X∞ k=−∞
h(m−kL)x(k)
This equation also has a form similar to a convolution in which only one out of everyLsamples of the filterh(n)is used in the computation of a given output; that is, multiplication by the zero-valued samples of w(n) are not
)
|Y(ejω´| )
|W(ejω´| X(e )jω
| |
π/L
ω´
ω´ π/L
x(n)
y(m) w(m)
0
0 π
π 2π
2π 2π
π ω
(a)
(b)
(c)
Figure 2.3: Typical waveforms and spectra for interpolation by integer factor 2.
included in this equation. As in the decimator, this is a periodically time- varying system in which different values of h(n) are periodically used for the computation of each output. Although the filter is specified at the high sampling rate F0 =LF, in practice, it is implemented at the low sampling rate F for efficiency. The decimation filter used in this system is designed with a multi-stage approach. 1
2.1.1 First stage
The first stage interpolates the signal by a small integer factor, normally four. It is done by inserting three zero-samples between each sample after the input register, increasing the sampling frequency by four. Then the signal is low-pass filtered to smoothen the signal. The low-pass circuit can usually be very simple [6], and since the word rate is low, the bits can be processed serially rather then in parallel. Another ting is that the word lengths of the coefficients of the FIR filter are short enough that dedicated multiplier circuits can be used rather then shard ones.
During the simulating of the system and the testing on the Altera chip, the FIR filter is assumed to be ideal and thus it has been left out. The output signal from the ideal FIR filter is just the input signal with a sampling frequency four times higher. In this thesis the first stage of the interpolator is assumed to have no effect on the signal and is therefore ignored, but the
1The phrase up sampling and interpolation ratio/factor means the same, increasing the sample rate.
Z-1 Z-1 Z-1 Z-1
Clock frequency: fs L fs
Figure 2.4: This is how a second order sinc interpolating filter is implemented where the interpolation(upsampling) factor is L.
ω
|U(j )|
(a) (b)
f ω
s Z-1
U(Z)
Figure 2.5: A) shows the block diagram of one stage of the differentiator and b) a graph of its frequency response.
use of a two-stage interpolator is important.
2.1.2 Linear interpolator - SINC
With the multirate and/or multistage design considerations one of the most effective illustrations of matching design simplicity is given by the use of sincK filter for the high rate stage of an interpolator. The frequency re- sponses associated with the linear interpolation circuit and the up sampling stages are a sampled sincK function [6]. The sincK filter of a interpolator is implemented by cascading K stages of differentiators operating at the low sample rate, followed by K stages of cascaded accumulators operating at high sampling rate. A second order sinc2 filter is shown in figure 2.4. Since the sincK filter does not need a digital multiplier it is much more suited for hardware implementation. It also utilizes a base 2 wrap-around arithmetic which is inherently stable [9].
To deduce the transfer function for a sincK interpolation filter the fre-
quency response of each stage is shown in figure 2.5 and 2.7. Figure 2.5 shows the block diagram of the differentiator and a graph of it’s frequency response. The Z−1 block delays the word one clock cycle, and the output U(Z) is a difference of the present word minus the delayed word. This will result inn that only the difference between one word and the previous will pace through. And if there is no change in the signal the output will be zero.
The mathematical representation of it, is shown in this equation U(Z) = 1−Z−1
which is one building block of the sinc filter. Generally where the order of the filter isK, sincK, the equation will be
U(Z)K = (1−Z−1)K
The next stage in the interpolation is the up sampling stage, shown in the figure 2.8 as the third block with the up arrow and L as the up sampling ratio. In figure 2.4 the up sampling stage is explained/shown as the increase of clock frequency between the differentiators and the accumulators.
fs−→Lfs
The new signal is formed by putting L−1 zeros in between each word.
The frequency response of the differentiator with increased sampling rate is shown in figure 2.6 with an up sampling ratio ofL= 8. This function shows the result whenU(Z) is sampled up
V(Z) =U(ZL) = 1−Z−L
and when it is used in a sincK filter with K blocks of differentiators before the interpolation
V(Z) =U(ZL)K = (1−Z−L)K
The next stage is the accumulator and a block diagram of it is on fig- ure 2.7 together with its frequency response. As in figure 2.5 the Z−1 block delays the word one clock cycle, but the output W(Z) is the accumulation of the present and the delayed word. This will make the output be constant as long as the input is zero, but with an input of any kind the output will rise. The transfer function of one accumulator stage of the sinc filter is
W(Z) = 1 1−Z−1
and for K accumulator stages the function will be W(Z) = ( 1
1−Z−1)K = 1 (1−Z−1)K
2π ω fs
ω
|V(j )|
Figure 2.6: Frequency response when the signal from the differentiator is up sampled 8 times.
W( )Z
ω
|W(j )|
ω (b)
fs (a)
Z-1
Figure 2.7: A) shows the block diagram of one stage of the accumulator and b) a graph of its frequency response.
U(Z) U(Z) L W(Z) W(Z)
V(Z)
Y(Z)
Figure 2.8: This is the block diagram of thesinc2 filter with an interpolation factorL
In figure 2.8 it is shown how the block diagram of akth order sinc filter will be. The Transfer function of a sincK will then be
Y(Z) =V(Z)∗W(Z)K = (1−Z−L)K∗ 1
(1−Z−1)K =
1−Z−L 1−Z−1
K
The frequency response where ω= 2πff
s is therefore Y(ejω) =
1−e−jωL 1−e−jω
K
(2.1)
= ejωL2 ejωL2
!K
ejω2 ejω2
!K
1−e−jωL 1−e−jω
K
(2.2)
=
ejω2
ejωL2 −e−jωL2 ejωL2
ejω2 −e−jω2
K
(2.3)
By using tht Euler’s relation which states that ejθ = cosθ+jsinθ which gives 2 cosθ=ejθ+e−jθ and2 sinθ=ejθ−e−jθ which applied to equation 2.3 is
Y(ejω) = ejω2 ejωL2
!K
2jsin(ωL2 ) 2jsin(ω2)
!K
(2.4)
= ejω2 ejωL2
!K
sin(ωL2 ) sin(ω2)
!K
(2.5)
The fraction
ejω2 ejωL2
K
will only give a phase shift to the frequency response and therefore it can be removed, which then makes the frequency response
Y(ejω)= sin(ωL2 ) sin(ω2)
!K
IfLis even then the frequency response hasL/2spectral zeros in the area from[0, π], and ifLis odd it hasdL/2e −1where dL/2emeans it is rounded upwards [9]. These spectral zeros are at frequencies that are multiples of the interpolated sampling frequency ωi, that is
H(ejω) = 0 ω=nωi n={1,2,3,· · · ,bL/2c}
Sometimes there is a desire to have no change of total power in the frequency spectre before and after thesincK filter. Since the summation of the frequency components from0−2πis the total power, and thesincKfilter
2l
mod ( ) mod ( )2l
Neg. Pos. 44
44
44 45
sum
outp outp
a) b)
diff
Figure 2.9: This figure shows the modulo function and what it does with the signal. a) illustrates that the difference might make the signal negative (diff) but the next stage sees it as the modulo (outp). b) shows what the next stage sees when the output of the summation is bigger then the number area used.
increases the number of components by a factor ofLK, then the frequency response with constant power is
Y(ejω)= 1 L
sin(ωL2 ) sin(ω2)
!K
The modulo 2 arithmetic
The architecture of thesincK filter utilize a two’s complement wrap-around or modulo 2 arithmetic. In the differentiator the wrap-around happens when the input is a large number followed by a small number, the sum will be negative. Since the sum is represented as an unsigned word the negative sum will in the next stage be seen as positive. The sum will be interpreted as a number which has wrapped around its number area, or as the modulus2
outp= mod2l(sum)
where l is the word length in the sinc filter, that is also shown in figure 2.9 a).
In the accumulator when the adder gets an overflow it has reached a value larger then the number area, then the carry out bit is ignored and thereby the value has wrapped around its number area. This is mathematically described with the modulus function as
outp= mod2l(dif f)
where l is the word length in the output and sum is the summation in figure 2.9 b) whereoutp is what the next stage sees of the summation.
The wrap around will generate an error to the signal but these two mod- ulus functions affects the signal in opposite ways. Since they are the inverse
2Modulus is the remainder after division: mody(x) =x−ybx/ycfor y6= 0wherebc mean rounding the element to the nearest integer towards minus infinity.
mathematical equivalence of each other the error they generate each will be evened out and the result is a filtrated signal of higher sampling frequency.
Input sinc word size relation
A relationship between the input word size and the sinc filter word size is outputwordsize =inputwordsize+ (K−1) log2L (2.6) To verify this equation for a second ordersincis easy because in a worst- case scenario the fist sample is maximum input (2b−1). This sample will be passed through the differentiators, and the first accumulator will act like a holding register and hold the value for the number of times over sampled (L), which will not increase the sample value. Then on the second accumulator the word will be accumulatedL times. This will give the maximum value
L∗2b−L which gives
2b+log2L−1
and since 2b+log2L >> L the maximum value must be represented by b+ log2Lbits.
This relationship gives the designer the least amount of bits needed to design a sinc filter. It can be designed with more bits but the output will not use them. The internal registers will on the other hand use these extra bits but without effecting the output.
The output of the sinc filter has a much larger number area then the input and since the filter cannot introduce more information to the signal, the least significant bits are not needed. To remove the least significant bits from the signal the output can be divided by 2(K−1)log2L. However this has not been done in this converter system.
This will also reduce the power increase introduced by the filter but if constant power is needed it can be achieved by dividing the output withLK. Implementation
The first ordersincK filter can be implemented in two different ways. The first way is described earlier and follows the definition of sinc filters, like figure 2.4. The second way is the sample and hold function, because a first order sinc filter is the equivalent. This function increases the sampling rate by repeating each sample a number of times to create the new signal. This can be used in the design ofsincK functions of one higher order with little effort. The sample and hold function is placed in the center of the filter between the low sampling rate stages and the high rate ones.
MSB
Z-1 Z-1
25
24 1 1
Figure 2.10: The first order pipelined ∆−ΣDA converter.
The start process of the sincK filter
When looking at the Sinc filter it is hard to understand how a dc value is passed through, because the output of the differentiator is only the changes in the signal not its amplitude. When thesincK filter start its initial state is zero. The first value on the input will pass through the differentiator stages unchanged. The accumulator stages will use this value to generate a value in the new number area relative to the input value.
2.2 Modulator - The new pipelined ∆ − Σ DA con- verter
The modulator used in this system is the 1st order pipelined∆−ΣDA with its block diagram shown in figure 2.10. This design is mathematical equivalent with the conventional converter and therefore it is a new design of the old one. A feature of this design is that it is easily scalable in order, and with no global feedback loops this will make the design easier and simpler.
The pipelined ∆−Σ modulator consists of first a accumulator with a feedback loop as shown in figure 2.10. The word size is one bit bigger at the output of the accumulator and the feedback then on the input. Then there is a quantization where only the most significant bit is on the output. The output of the quantization then goes to a differentiator that will subtract the present with the previous bit. When the word size of the output of the quantizator is one then a xor port will carry out this operation.
2.2.1 Scaleable in order
Since there is no global feedback loops, the work of designing a converter of higher order is simpler. The figure 2.11 shows a block diagram of how the higher order pipelined converter is. Increasing the number of accumulators in front of the quantizator and differentiators behind it increases the order.
One accumulator and one differentiator gives a modulator of first order, while two accumulators and two differentiators makes it second order, and so on.
The number of accumulators and differentiators sets the magnitude of the order. When scaling the order of the old or traditional one it gets more complex.
Z-1 Z-1 Z-1 Z-1 MSB
Figure 2.11: This figure shows the pipelined∆−ΣDA converter of a higher order.
2.2.2 Pipelined
In the second chapter it is shown the block diagram of a conventional first order ∆−Σ DA converter, both in text and figure 1.5. When compared to the pipelined converter the big difference is that this one has no global feedback loops. This will make it possible to implement it in a pipelined way by placing D-flip-flops between each stage. When a function is implemented in a pipelined way, its clock frequency can be increased. This will on the other hand give the signal a delay for each delay implemented.
2.2.3 Accumulator word length
The argument deciding the word length of the accumulator is the number of output bits and the word length of the input signal. The number of bits in the quantizator plus the word length of the input signal gives the accumulators bit sice.
2.2.4 Pattern noise
When the input is a dc-signal then the output will oscillate between two levels keeping the mean value equal to input. The oscillation will be a repeating itself after a period. And if the frequency of this period lies in the signal band, the modulation is noisy.
In the article "Oversampling methods for A/D and D/A conversion"[6]
there is a graph where the in-band rms modulation noise depends on the dc input level. Where the ∆−Σmodulator has quantization levels at ±1 and an oversampling ratio of 16. This figure gives a good impression of at what input and how great the in-band rms modulator noise is. So the input can be limited to an area where the in-band noise is low.
The mathematical expression [12][13] for the noise from∆Σ modulation with dc input is
y(t) =Y0+X
l
X
k
sin(πlx0)
πl exp(jπ+lx0+k
T t) (2.7)
wherex0= (x−Y0)/∆and xis the input level to the modulator and Y0 the adjacent quantization level. This equation gives a good description of the pattern noise[12]. The simulation of the pattern noise will give an idea of how good the modulator is.
x Output levels
Quantization error
l Thresholds
q(x)
Figure 2.12: The q(x) quantizer function
2.2.5 Mathematical equivalent
Figure 2.12 shows the Z-transform representation of a traditional discrete- time first-order∆−Σmodulator (DSM). To show the mathematical equiva- lence between the traditional and the pipelined first-order delta-sigma modu- lator it is necessary to give an exact mathematical definition of the complex quantization function Q, defined by Q[U(z)] = Z{q(un)}. In this discus- sion the quantization levels are few, typically two levels, and the unity-gain quantization functionq(x) will therefore be defined as
q(x) =x−modl(x) (2.8) where the quantization thresholds are multiples ofl. And modl(x)gives the reminder ofx after the division withl. The definition of modl(x) is
modl(x) =x−lbx
lc (2.9)
wherebcwill rounds to the nearest integer towards minus infinity. By putting equation 2.9 into equation 2.8 this is what you get
q(x) =x−x+lbx
lc=lbx
lc (2.10)
The property of the quantization function used in proof of equation 2.16 is q(x1+x2) =q(x1) +x2 if q(x2) =x2. (2.11) where q(x2) =x2 means
q(x2) =lbx2
l c = x2 (2.12)
bx2
l c = x2
l . (2.13)
And this equation means that x2 is dividable by l if q(x2) = x2. Using the definition of q(x) equation 2.11 can be written like this
q(x1+x2) =lbx1+x2
l c=lbx1 l +x2
l c (2.14)
and by using the
The complex quantization function, defined with
Q(X(z)) =Z{q(xn)} (2.15) will then have the following property
Q(F(z) + z−aG(z)
(1−z1)b) =Q(F(z)) + z−aG(z)
(1−z1)b) if q(gn) =gn. (2.16) F(z) and G(z) are hereZ-transformed representations of the general signal fn andgn, with aandb as positive integers.
The proof of this is as follows: From equation 2.8, the quantized sum of two integers I1 and I2 will be
q(I1+I2) =I1+I2−modj(I1+I2). (2.17) When q(I2) = I2 then modj(I2) = 0 given from of equation 2.8, and this gives then that modj(I1+I2) =modj(I1). This means that the equation 2.17 may be written as
q(I1+I2) =I1+I2−modj(I1) =q(I1) +I2. (2.18) When equation 2.18 is valid for every I1 and I2 where q(I2) = I2, then it will also be valid for every sequencefn andln when q(ln) =ln, which gives q(fn+ln) =q(fn) +ln if q(ln) =ln. (2.19) TheZ-transform of equation 2.19 together with the linearity property of the Z-transform shown in appendix 3and the definition of Q(z) we will have
Q(F(z) +L(z)) =Q(F(z)) +L(z) if q(ln) =ln. (2.20) If we letln be the delayed, accumulated and quantized sequencegn, thenln
will be a quantized sequence. When gn is delayed a-times and accumulated b-times, theZ-transform of ln may be expressed as
L(z) = z−aG(z)
(1−z−1)b. (2.21)
When inserting equation 2.21 into equation 2.20 the result is the resolving property equation 2.16. The resolving property is a vital part when showing
Z-1 U(z) Q( )
Y(z) X(z)
Figure 2.13: Z transform representation of the traditional first-order DSM.
Z-1
Q( ) Z-1
U(z)
Y(z) X(z)
Figure 2.14: Alternative design of the traditional first-order DSM shown in figure 2.13.
the mathematical equivalence between the traditional and the pipelined first order∆−Σmodulator.
Figure 2.13 shows the Z-transform of a traditional first order discreet time DSM. Figure 2.14 is the same function as the one in figure 2.13 but it has no delay onX(z). By using figure 2.14 it is possible to show the mathematical equivalence between the traditional and the new pipelined modulator. It is done by first getting an expression for Y(z) from the figure 2.13
Y(z) =Q(U(z)) (2.22)
but U(z) can be described as
U(z) =z−1U(z) +X(z)−z−1Y(z) (2.23) U(z)−z−1U(z) =X(z)−z−1Y(z) (2.24) (1−z−1)U(z) =X(z)−z−1Y(z) (2.25) U(z) = 1
1−z−1X(z)− z−1
1−z−1Y(z) (2.26) With the definition of the complex quantization function in equation 2.15 the outputY(z) would be
Y(z) =Q 1
1−z−1X(z)− z−1
1−z−1Y(z)
(2.27)
3Her skal det være en ref til det som står i 256-boka på side 173
Q( )
X(z) U(z) Y(z)
Z-1 Z-1
Figure 2.15: This figure shows the mathematical equivalent design of fig- ure 2.14.
By using the resolving property defined equation 2.16 on equation 2.27 we get
Y(z) =Q 1
1−z−1X(z)− z−1
1−z−1Y(z)
(2.28) and reducing the equation
Y(z) = (1−z−1)Q 1
1−z−1X(z)
(2.29) This equation describes a new circuit shown in figure 2.15 which is dif- ferent from the one in figure 2.14 but has the same mathematical properties.
The new circuit works by first integrating the signal then quantization it and finely derivate both the signal and the quantization error, to restore the signal. When the quantization noise is derivated its frequency specter gets shaped and shifts the noise out of the signal band.
Figure 2.15 can be interpreted in a continuous-time way. This way the accumulator is an integrator with a gain of1/Ts and the differentiator is a derivator with a gain ofTs[2]. Where Tsis f1
s and this means that the signal has a gain of1/Ts which the quantization noise doesn’t have4.
These two effects on shaping the quantization noise improves the SQNR5 by≈6dB for each doubling of the sampling rate.
2.3 Zeropadding
When the input on a transistor change, the change on its output is delayed.
This delay shown in figure 2.16, is called slew rate. This slew rate will make the average value of a single high bit lower then consecutive high bits.
The modulated signal of a maximum value consists of many consecutive ones and its average value will not be effected much of the slew rate. But the modulated signal of a half of maximum value consists of many single ones and its average value will be affected by the slew rate. The average of a modulated value half of maximum, is less then half of the average maximum
4fs is the sampling frequency.
5SQNR means Signal-to-Quantization-Noise-Ratio
Innput
Output VDD
t
Figure 2.16: The switching characteristics of an inverter.
Without zeropadding With zeropadding
Figure 2.17: This graph shows the switching characteristics of a transistor with and without zeropadding.
value. This difference will make the converter nonlinear but with zeropadding will the effect of slew rate be reduced.
Zeropadding means adding a zero sample between each sample in the modulated signal shown in figure 2.17. The nonlinear effect from the slew rate will be reduced when there are no consecutive ones on the output of the modulator. The average output of the modulator with zeropadding is half relative to a modulator without zeropadding. The increase in linearity improves the SNR more then the loss in signal amplitude reduces it.
Chapter 3
Component, system and hardware simulating
Simulation is an important tool to determine what the effect of the different parts of the system was when they constitute a converter system. Some of the different properties that were simulated in this thesis was the modulator and its pattern noise, the sincK filter, the whole system and simulation of its VHDL code.
For simulation the programming languageCand the program Matlab[15]
were both used. The simulation could be done with only Matlab, but since thef or-loop in Matlab was slow it was implemented inC instead.
The Blackman-Harris-Hoodie window(A.1) used in the fast fourier trans- form was a cosine window like the Blackman window(A.9). While the Black- man window has only two cosine terms the BHH windows have six.
The bandwidth of interest was500Hzthat gives a sample rate of1KHz.
With an intermediate interpolation stage the sample rate was increased by 4 times to4KHz. When implementing the system on the chip the input clock was at8M Hz that was divided down 211 times, which gives a frequency of 8M Hz/211= 3906,25Hz. This will assure the clocks both the differentiators and the accumulators to make their transitions at the same time. This sampling frequency was used for the input signal in some of the simulations.
3.1 Simulation of the pipelined ∆ − Σ DA modulator
This simulation of the modulator stage shows the result when an ideal si- nusoidal wave was applied to it. The actual modulator was implemented in C to make it as fast as possible. The fast fourier transform computation and signal visualization were made with the Matlab program. The C- and Matlab-code is in the appendix B.
Figure 3.1 shows the frequency specter of the output signal. One obvious pattern noise effect in the plot starts at approximately 250kHz. Its power
101 102 103 104 105 106
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20 0
Normalized Power Spectral Density (dB)
Frequency (Hz) S/(N+D) = 107dB (17.8bit)
Figure 3.1: A 222 point simulation of the pipelined DSM. The signal to noise ratio (S/N+D) was calculated with a bandwidth of 500Hz. The signal frequency was 325Hz with a sampling frequency of 1024kHz
specter density was normalized and plotted in decibel versus the frequency in a logarithmic scale. The amplitude of the input sinusoidal signal in this simulation was 90% of maximum. The bandwidth of interest was bw = 500Hz and the sampling frequency was fs = 1024kHz while the signals frequency wasf re= 325Hz. The numbers of samples in the simulation was 222 = 4194304 which gives a frequency spectre of 221 = 2097152 points.
A more visual representation of what the signal looks like are shown in figure 3.2. It’s the low pass filtered signal from the modulator and it shows one wavelength that are 3151 points. The low pass filter used was a 5th order Chebyshev type two low pass IIR filter. The stopband was at2500Hz and the stopband ripple was70dB down.
From the second figure(3.2) it was obvious that a sinusoidal signal was achieved. The frequency specter in figure 3.1 showed clearly the noise shaping effect of the∆−Σ modulator. The increase in noise or steepness was about 20dB/decade, which is expected from a first order modulator. The resolution of the output signal or signal/(noise+distortion) was when using a bandwidth of 500Hz, approximately 18bit. The graph drawn in black is below the bandwidth of 500Hz while the one drawn in red is above the bandwidth.
0 2000 4000 6000 8000 10000 12000 0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Amplitude level
Sample number
Figure 3.2: One wavelength of the low pass filtered signal from the pldsdm.
Numbers of samples shown are fs/f re≈3151
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−50
−40
−30
−20
−10 0
8 fimes oversampling
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−50
−40
−30
−20
−10 0
128 fimes oversampling
Total in−band noise power (dB)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−50
−40
−30
−20
−10 0
1024 fimes oversampling
DC level min−max
Figure 3.3: 1000 point pattern noise simulations of the pipelined DS modu- lator with different oversampling ratios. The bandwidth of interest is 500Hz and dc level input value goes from zero to maximum (231).
3.2 DC sweep simulation - Pattern noise
Pattern noise described in section 2.2.4 gives a good description of the mod- ulator. Figure 3.3 shows three 1000 point simulations at different oversam- pling ratios where the total noise power plotted at different dc inputs. The oversampling ratios are 8, 128 and 1024, and the bandwidth of interest is 500Hz. The input level goes from zero to max value (231)1. This simulation was programmed in C- and Matlab-code shown in appendix C.
3.3 Amplitude scan
This simulation was done to shows how the signal to noise ratio changes with the input signal amplitude. One simulation is done with white noise on the input of the modulator and the other is done without. Figure 3.4 shows the result of two 1000 point simulation where the amplitude sweeps from
1The implemented modulators max input value is 244, but because of the hardware used for simulation(Sisc architecture) max integer input value is231
10−3 10−2 10−1 100
−10 0 10 20 30 40 50 60 70 80 90
Amplitude of the input sine wave(dB)
Signal−to−noise ratio (dB)
Amp scan w/noise Amp scan
Figure 3.4: This figure shows the SNR of a modulated sinusoidal signal plotted with respect to its different input amplitude levels. This amplitude scan was done both with and without white noise added on the input signal.
The bandwidth is 500Hz and the signal frequency is 150Hz with a sampling frequency of 1024kHz.
2∗10−4kto k, wherek= 231 is the max value. The input signals sampling frequency was 1024KHz and the signal frequency was 150Hz. 218 = 262144 samples were used to calculate each point. The noise added was a random integer in the area from 0 to 1000, and this has an effect on the 9 least significant bits. This simulation was programmed in C- and Matlab-code shown in appendix D.
The curve of the amplitude sweep without added white noise was almost straight and increases by approximately 30dB/decade. This is not expected from this modulator but is assumed to be pattern noise effects. The other curve with added white noise was smoother and increased by approximately 20dB/decade, and this is expected from a first order modulator.
3.4 Simulation of the sinc
3filter
To understand the whole system and how the signal was affected by the different stages it was important also to simulate the interpolation stage.
