Test of Initial Design

This section describes how the iterative approach to improve the design was carried out by testing the initial design described in this chapter and by using simulations which are briefly described next chapter (see 6.2). Table 5.7 shows the final device dimensions. Even though the circuit shows the expected behaviour in terms of bias currents and voltages, as well as sufficiently high gain and stability over the corners for DC operating point anal-yses, it did not fulfil all the requirements of section 5.6. The Monte-Carlo simulations showed that the sensors input offset voltage showed a variance of 3σ higher than the re-quirement (see chapter 5.6.5). The current density ratio showed also high variations, as well as the gain. In Cadence, it is possible to see which device contributes to mismatch between devices. For example, it was shown that the current mirror devices M12and M13

have a large effect on the variation of the input offset voltage. Therefore, in an iterative way, the design was simulated and improved by checking which device affects which pa-rameter the most and which devices mismatch can be reduced.

The current mirror devices M12 and M13 showed great influence on the input offset volt-age. This means that their matching needs to be improved. In chapter 5.7.3, the equation 5.65 for the matching of current mirrors was used, it is not surprising that the mismatch is not quite as expected. This is due to the fact that the process parameters A_Vt0and A_K that were used are not for this process design kit. Thus, to increase the matching of the devices which is mostly dependent of the threshold voltage, the area of the transistors was increased and at the same time the overdrive voltage was increased to lower the effect on the input offset voltage. Therefore, the new overdrive voltage for all current mirrors is set to 200 mV and the area is increased from 96μm²to around 150μm². This results in a new width and length for all PMOS current-mirror devices. The values can be found in table 5.7.

In addition, it was tried to lower the input offset voltage and to improve the current den-sity ratio of the bipolar core by increasing the area of the NMOS devices in the op amp.

However, increasing the area increases the capacitances which slows down the circuit.

Nevertheless, since temperature usually does not change very rapidly it is acceptable to have low speeds. Therefore, all NMOS devices were changed to larger areas while keep-ing the overdrive voltage the same. It was found after runnkeep-ing MC-simulations that the current density ratio and the offset voltage improved, however, for temperatures at the end of the range the current density ratio got significantly worse. This led to the decision to keep the NMOS devices as before. The device dimensions are shown in table 5.7.

The differential input pair greatly affects the input offset voltage, however, since chopping

is used these two transistors are kept the same.

All of the current mirror devices are exceeding the length limit for a single device which is set to L = 30μm. Therefore, it was necessary to ”cascode” two devices. When two de-vices are biased with the same gate voltage they behave like one transistor with the length of both devices summed up. This is called a ”poor man’s” cascode ([10], p. 88).

Table 5.7:Final aspect ratios of all devices.

Device Width [μm] Length [μm]

Chapter 6

Simulation

6.1 Introduction

Chapter 6 presents the simulation of the circuit, and afterwards the results. It starts by explaining the different analyses that were conducted in section 6.2. Afterwards, the per-formance of the analog front-end is presented in section 6.3.

6.2 Simulations

To test the circuit a variety of simulations are available in Cadence Virtuoso but only a few are conducted to check the correct operation. A very brief overview of the simulations that were used is given

The DC operating point analysis checks the bias point of the circuit, where it is possible to check all the assumptions made about the circuit, such as bias currents, voltages, resis-tances or capaciresis-tances.

The AC analysis is used to test the circuit to see how it reacts to a small signal stimulus around the DC operating point, which includes, for example, the frequency response of the circuit, as well as the bandwidth and amplification. Similarly, the stability analysis can be used to check the frequency response of the system and whether it is stable or not.

The transient analysis computes the transient response of the circuit over a specified time interval.

The noise analysis analyses the noise contribution of every device and computes the total output referred noise.

Monte-Carlo (MC) simulations are used to simulate the random effects of processing spreads and to receive an overview of statistical variations of the devices parameters and how mismatch of the devices affect the performance.

Corner simulations are used to test the circuit for extreme cases in terms of device pa-rameters, such as thinner gate oxide or lower threshold voltage. These extreme cases can occur due to process variations. There are four corners and the nominal ”corner”, shown

in figure 6.1. These corners are named FF, SS, FS, SF and NN, where the first of the letters stands for the NMOS and the second letter for the PMOS. They describe the speed of the MOS-devices. Therefore, the FF-corner includes fast NMOS and fast PMOS devices and so on ([10], p. 709). All of the mentioned simulations are also conducted over all corners.

Figure 6.1:Process corners and speed of NMOS and PMOS devices ([10], p. 709).