Mitigation of Parasitics

A final issue introduced by the reduced die size comes from the aforementioned low cur-rent ratings. As a result of the low curcur-rent ratings, several chips will need to be paralleled in order to reach desired power levels. This will have an adverse effect on heat spread-ing. Hence, an optimized distance between chips needs to be developed in order to have sufficient heat spreading while maintaining minimum distance between chips [15].

2.2.2 Mitigation of Parasitics

As was remarked in subsection 2.1.2, replacing Si with SiC enables the production of power devices with a higher maximum switching frequency. Although this is a desirable feature, it does bring along some challenges, since increasing the_dt^diand^dv_dt while keeping parasitic inductances and capacitances unchanged will lead to increased voltage overshoot, parasitic turn-ON in half-bridge modules, and ringing. In a typical semiconductor power module, there are three parasitic inductances of note: Commutation loop stray inductance, Lσ, gate loop inductance,LG, and their mutual inductance,Mσ−G. These parasitics can prove to be a significant detriment to the performance of a SiC power module. The over-voltages induced by the parasitics might end up exceeding breakdown voltage levels if the stray inductance levels are not reduced from their typical magnitude in an off-the-shelf package [15].

The main way to reduceL_σandL_Gis to minimize the current loop in the module and in the gate driver, respectively.The gate driver loop can be reduced by using module integra-tion, where associated components which are usually placed outside of the power module are put inside the package. One of these components is the gate driver, and placing the

of wirebonds, and instead employs planar interconnection techniques using an additional substrate. The additional substrate is placed directly on top of the chips, and copper traces on the substrate are used for routing and interconnection purposes. This allows for a vertical current flow between the two substrate planes, which can lead to a 30%decrease in stray inductance by decreasing the interconnect paths. This structure is also better for cooling purposes, since it reduces the thermal resistance of the module, and allows for double sided cooling, as mentioned in subsection 2.2.1. The Chip-on-Chip solution, shown in Figure 2.14b, places chips directly atop of one another in order to further reduce the stray inductance of the module. This structure has been shown to reduce the stray inductance of a half-bridge module to as little as 0.25 nH, which is a reduction of two orders of magnitude in comparison to the current off-the-shelf packaging structures. The only way to reduce the stray inductance further is to use wafer-level packaging, which increases the complexity level of the packaging considerably [14, 15].

(a)Wireless (b)Chip-on-Chip

Figure 2.14:Example of different structures used to minimize stray induction [14]

An important issue related to the fast switching speed of SiC MOSFETs is how it relates to paralleling several chips. The reason for paralleling devices is generally to increase the current rating of the power module, and as such, it is imperative to keep the current level in all the paralleled devices balanced. In this way, no single die will be overloaded.

Yet, parasitics between the paralleled chips can lead to current imbalance, and demands symmetrical layouts of the paralleled devices to mitigate the issue. But, with increased switching speed the tolerance for asymmetry is lower, making it more challenging to pro-duce a module that is able to maintain current balance between its constituent components [14, 23]. Figure 2.15 shows an example of how asymmetric inductance distribution might affect the current sharing during switching instances. The set-up from the example con-sisted of 10 168 A rated SiC MOSFET half-bridge modules in parallel, where each module

consisted of 5 SiC MOSFETs in parallel per phase leg, for a total of 50 SiC MOSFETs per phase leg. A steady-state analysis of a single phase leg in a step down converter using a switching speed of 20 kHz showed that even without a perfectly uniform current distribu-tion, the largest deviation from the average temperature of 38.73 °C was 1.5 °C, or 3.87% [23]

(a)Turn-ON (b)Turn-OFF

Figure 2.15:Current distribution in 10 parallel SiC MOSFET modules during switching [23]

It is also worth noting that the Miller capacitance, the parasitic capacitance between the drain and gate of the SiC MOSFET, might lead to an accidental turn-ON in a half-bridge configuration or similar. If the charge in the capacitor leads to the voltage across the Miller capacitance exceeding the threshold voltage of the device in question, an accidental turn-ON will occur. The charge rate of the capacitor is the same as the current supplied to the capacitor, and this current is determined by the capacitor equation (2.5). The larger the

dv

dt, the faster the capacitor is charged, and the more likely it is for an accidental turn-ON to occur [15].

i=Cdv

dt (2.5)

If this proves to be a problem, it can be mitigated using a Miller clamp, as seen in Fig-ure 2.16. This allows the current to bypass the gate resistor by turning on the transistor CL during turn-OFF, significantly reducing the voltage drop across the gate. As a result, it becomes unlikely for a parasitic turn-ON to occur [24].

Figure 2.16:Gate driver using Miller clamp [24]