pcie 3.0 device using an x1 connection, the actual bandwidth is approximately 1.97 GB/s or 985 MB/s in each direction.
2.2 Interface Lineage
Many different solutions to interfacing a storage device have emerged over the years. Interfaces such as the FD-400 8 inch floppy disk driver, the Enhanced Small Device Interface (esdi), and most proprietary interfaces, have not sur-vived, while others, such as Integrated Drive Electronics (ide) andscsibased interfaces, have remained and are still widely used. Here follows a description of the interfaces that have stood the test of time, and are still in use.
2.2.1 Small Computer System Interface
Small Computer System Interface (scsi), originally named Shugart Associates Systems Interface (sasi), was developed in the years 1978–1981 by the Shugart Associates Company, who based it on the Selector Channel in IBM-360 com-puters. In 1986, only few years after being publicly disclosed in 1981,sasi became anansistandard and the name was changed toscsi[30]. Thescsi standard defines how computers physically connect with and transfer data to and from peripheral devices. The uses ofscsirange from Compact Disk (cd) drives and printers tohdds, where the latter is the most common.
scsiuses abus topology, meaning that all devices are daisy-chained linearly, as depicted in Figure 2.5. Each bus supports up to eight devices, but expanders can be used to allow morescsisegments to be added to a scsidomain. A scsibus must be terminated at the end, such that the bus appears electrically as if it is infinite in length. Any signals sent along the bus appear to all devices and end in the terminator, which cancels them out, such that there are no signal reflections that cause interference [31], as shown in Figure 2.6.
2.2.2 Integrated Drive Electronics / Parallel-ATA
Integrated Drive Electronics (ide), also referred to as Parallelata(p-ata), is the the result of further development of the Industry Standard Architecture (isa) interface developed for use in IBM’s Personal Computer at(pc/at)—
a bus that supported a parallel transmission of 16 bits at a time. The ide channel was designed as a purehddinterface since other proprietary interfaces already existed for devices such ascd-roms and tape drives. However, during
SCSI bus ID 0
ID 1
ID 2 ID 4
ID 3 ID 5
Figure 2.5:Thescsibus is a linear daisy chain of up to eight devices, but expanders allow morescsisegments to be added to the domain.
Terminator
1
2
Figure 2.6:Ascsibus must be terminated to avoid interference. A terminator stops the signals at the end of the line, and makes it appear as if the bus is infinite in length. The figure illustrates an unterminated bus (1) and a terminated bus (2). The terminated bus appears to be infinite in length, and avoids interference from signals that bounce back from the end.
the 1990’s, it became obvious that a single, standardized interface would be preferable to the proprietary interfaces.
Because the at Attachment (ata) command structure is incompatible with anything buthdds, theatAttachment Packet Interface (atapi) was developed to work on top of ide [32], which allows the ata interface to carry scsi commands and responses.atapibecame very successful, and is still used in modernsatainterfaces.
ProgrammedI/O
Early versions ofataoperated in programmedi/o(pio) data transfer mode, which occurs when thecpuinstructs access to a device’s i/o space for data transfer.piois relatively simple and cheap to implement in hardware, but has the disadvantage that thecpuis responsible for all data transfer, as illustrated in Figure 2.7. This means that thecpuconsumption increases proportionally with the transfer rate, potentially creating a bottleneck in the overall computer performance.
2.2 I N T E R FAC E L I N E AG E 15
RAM CPU Device
memory
Read / Write
Read / Write
Figure 2.7: Programmed i/o occurs when the cpu instructs access to a device’s i/ospace for data transfer. As the transfer speed increases, thecpuresource consumption increases as well.
In modern systems,piohas been replaced with direct memory access (dma), but is still implemented in interfaces that do not require high transfer rates, including serial ports, and the PS/2 keyboard and mouse ports.
Direct Memory Access
Unlikepio, where thecpucontrols and monitors data transfers to and from a peripheral device, the device operating in dma mode is programmed to perform data transfers to and from host memory on behalf of the cpu, as depicted in Figure 2.8. The only interaction required by thecpuis to grant the controller access to the system bus for data transfer.
RAM
Device memory controllerDMA
Read / Write Read / Write
Figure 2.8:Direct memory access allows a peripheral on the system bus to perform reads and writes to host memory on behalf of the cpu. The cpuis free to perform other tasks while data transfer is performed, and is notified by the device via interrupts when the transfer is complete.
Modern pcie devices can be configured as bus masters, allowing the dma controller to initiate transactions without involvement from thecpu. While
data transfers are handled by the controller, thecpuis free to perform other tasks, and may be notified of any changes in the memory area governed by the peripheral through interrupts [33].
2.2.3 Serial-ATA
Serial ata (sata)-600 is the result of a continuous effort to improve an ex-isting interface, and offers a theoretical maximum speed of 600 MB/s, while retaining backwards compatibility with earlier versions of the interface, such assata-300 [34]. Besides supporting high speed devices,sataalso supports hot swapping. Redundant storage systems benefit from this ability, as a faulty hddmay be replaced without having to disconnect the service.
Advanced Host Controller Interface
Advanced Host Controller Interface (ahci) is an application programming interface (api) that defines a mode of operation forsata. Theahcidevice is a pciclass device that acts as a data movement engine between system memory andsatadevices, providing a standard method of interaction between the host system and sata devices. This simplifies both detection, configuration, and programming ofsataandahciadapters [35]. Anahci device, or host bus adapter (hba), is required to be backwards compatible withataandatapi compliant devices, as well as both thepioanddmaprotocols.
Generic Host
Control Reserved Vendor specific Port 0 Port 1 ··· Port 31
Port Control Registers
Figure 2.9:ahci hbamemory consists ofGeneric Host Controlregisters that control the behavior of the entire controller.Port Controlregisters contain information for each port, such as two descriptiors per port, which are used to convey data.
The system memory structure described by ahci contains a generic control and status area, a pointer to a descriptor table used for data transfers, and a command list, in which each entry contains the information necessary to program a sata device. Figure 2.9 shows a simplification of this memory structure. In addition to implementing nativesatafeatures,ahcispecifies the support for 1 to 32ports, to which asatadevice can be connected. Theahci ports support simultaneous transmission of 32 commands.