O sistema desenvolvido e descrito nesta dissertação pode sofrer algumas alterações de modo a melhorar o seu desempenho, tanto em termos de hardware como em termos de software.
Na parte do hardware, o sistema pode ser compactado, juntando algumas placas. Por exemplo, pode-se juntar as placas de condicionamento de sinal numa só. Também se pode desenvolver uma fonte com tensões constantes de -15 V, -5 V, 0 V 3,3 V e 15 V que fique ligada ao barramento CC (Corrente Contínua) de modo a alimentar todo o hardware, e que no futuro possa ser utilizada com uma bateria de serviço num veículo
elétrico. A placa que contém o FPGA pode ser compactada numa placa que contenha apenas os recursos necessários para o controlador do motor, de modo que possa ser inserida num veículo elétrico.
Também se pode desenvolver um conversor CC-CC que permita aproveitar eficazmente a energia regenerativa e gerir o SOC (State-of-Charge) do sistema de armazenamento de energia, sendo necessário, para isso, observar previamente o efeito da travagem regenerativa, acoplando o motor a uma carga com inércia suficiente para isso.
A nível de software, os ganhos dos controladores PI (Proporcional-Integral) podem ser ajustados de modo a diminuir ou eliminar o overshoot da velocidade e estabilizar a amplitude das tensões e correntes em regime permanente. Quanto ao controlador, podem ser feitas várias otimizações no código Verilog de modo a diminuir os recursos utilizados e a aumentar a velocidade de processamento do controlador FOC. Por exemplo, pode-se utilizar sempre a representação em complemento para dois das variáveis, ao invés de se estar constantemente a passar de sinal e amplitude para esse modo de representação, e vice-versa, nas operações matemáticas. O número de estados de algumas máquinas de estados também pode ser reduzido.
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