Design and Validation of Two Single Event Latch-up Protection Solutions

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Single Event Latch-up Protection Solutions

Comparing a New Single Event Latch-up Test Circuit with the IDEAS IDE3466 Single Event Latch-up Detection Module

Jonas Birkeland Carlsen

Thesis submitted for the degree of

Master in Electronics and Computer Technology 60 credits

Department of Physics

Faculty of mathematics and natural sciences

UNIVERSITY OF OSLO

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Event Latch-up Protection Solutions

Comparing a New Single Event Latch-up Test Circuit with the IDEAS IDE3466 Single Event

Latch-up Detection Module

Jonas Birkeland Carlsen

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Design and Validation of Two Single Event Latch-up Protection Solutions

http://www.duo.uio.no/

Printed: Reprosentralen, University of Oslo

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Abstract

The focus of this thesis is single event effects in electronic circuits, and mainly single event latch-up. Various solutions for protecting against single event latch-up are discussed. On-site single event latch-up protection is becoming more relevant as more projects utilise low-cost components, potentially sensitive to radiation. Two circuits for such protection are verified and validated. Comparing these two solutions illuminate the diversity of on-site single event latch-up protection. The first of the circuits was developed for single event effects testing of electronic circuits. The circuit-board implements the functions required for an on-site latch-up protection, and was validated in both heavy ion and laser radiation hardness assurance tests. The test campaigns helped identify parameters relevant to single event latch-up detection and protection. The second solution explored was an integrated circuit developed by Integrated Detector Electronics AS. This circuit, the IDE3466, is implemented with a radiation-hardened design, and represents a safer, proprietary, but also more costly solution for on-site single event latch-up protection. The circuit was verified in the laboratory, as well as programmed for an experimental use case expanding its functionality beyond its intended application to include current sampling. The prospect of offering such a circuit commercially is also discussed by examining test results and the present commercial market.

Acknowledgements

I would like to direct my gratitude to Ketil Røed, Timo A. Stein and Dirk Meier, for their supervision and help along the way. Introducing me to this new world within electronics has given me so much. A big thanks goes to the people at IDEAS for their assistance in the work with the IDE3466 ASIC. I would also like to thank Sohail Mahmood for the cooperation during our two radiation test campaigns. Last but not least, I must thank my dearest Rikke for her patience.

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List of Figures

1 Annual sales in the global semiconductor market. Plotted using data from SIA [13].. . . 1 2 Illustration of the particle energies needed to penetrate the Earth magneto-

sphere.©IEEE 1988 [28], reprinted with permission. . . 5 3 Energetic particle precipitation in the Earth atmosphere creating neutrons

at ground level.©IEEE 2003 [25], reprinted with permission. . . 6 4 Simulation of particle fluxes in near-earth (interplanetary) space at maxi-

mum solar activity. Made using CREME96 [37, 38], which accounts for trapped protons, solar energetic particles and cosmic rays.. . . 7 5 Illustration of the Van Allen belts present around Earth. Picture from NASA’s

Langley Research Center [40]. . . 8 6 Observed variation in cosmic ray particles, caused by solar activity. ©IEEE

2008 [44], reprinted with permission. . . 8 7 Flux of protons withEkin ≥ 10MeV at 500 km altitude, generated with

SPENVIS [42]. . . 9 8 LET in a carbon absorber as a function of the incident particle’s kinetic en-

ergy. Irradiated particles from top to bottom: xenon, krypton, argon, oxygen and helium.©2012 Elsevier [64], reprinted with permission. . . 11 9 Cross section of CMOS structure irradiated by ionising particles. One NMOS

(left) and PMOS (right) device shown. . . 12 10 Parasitic BJTs present in a CMOS structure. One NMOS (left) and PMOS

(right) device shown. Adapted from Shoga & Binder [74]. . . 13 11 Parasitic thyristor in n-well CMOS, with high and low potential connected

through PMOS and NMOS transistors. Adapted from Troutman [73]. . . 14 12 Current-voltage characteristic of a PNPN junction, representing the ideal

thyristor without substrate and well resistances.©IEEE 1998 [77], reprinted with permission.. . . 15 13 N-well minority carrier guard ring collecting charges in bulk (top) and epi-

taxial layer (bottom) CMOS.©IEEE 1998 [77], reprinted with permission. . 15 14 Thyristor holding voltage as a function of anode-to-cathode (NMOS-to-

PMOS) spacing for different epitaxial layer thickness. ©IEEE 1996 [72], reprinted with permission. . . 17 15 Typical latch-up sensitivity curve plotting cross section as a function of heavy-

ion LET.©IEEE 2003 [20], reprinted with permission. . . 21

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16 Damage in metal layer of an integrated circuit after a single event latch-up of 2 A, seen as metal spheres on conductors.©IEEE 2002 [11], reprinted with

permission. . . 23

17 Circuit diagram of the SELTC. Thick grey lines indicate bus signals. SELTC power inputs (from supply) on the left, and power outputs (to DUT) on the right.. . . 25

18 Flowchart describing the design process. . . 29

19 Printed circuit board ready for component assembly. . . 30

20 Assembled single event latch-up test circuit (SELTC01).. . . 31

21 Plot of a 10 Hz sine wave sampled by the SELTC acquisition of one channel. 33 22 Plot of a 1 Hz sine wave sampled by the SELTC acquisition of six channels. . 33

23 Block diagram of set-up used for both radiation tests. . . 40

24 DUT and SOC FPGA boards mounted in the chamber rack during the heavy-ion test. . . 41

25 Set-up of functionality tests of the SEL Module. . . 43

26 Custom long length cable made for the SELTC’s outputs. . . 43

27 Vacuum chamber at the UCL HIF. . . 45

28 The UCL HIF vacuum chamber’s connector panel. . . 45

29 Plot of the SAMPA v4 current draw during xenon-124 irradiation ions. Sup- ply lines from top to bottom: test-board 2.5 V, digital 1.25 V, analogue 1.25 V, ADC-reference 1.10 V. . . 47

30 Plot detail of the SAMPA v4 2.5 V supply line current during xenon-124 irradiation. . . 48

31 Plot detail of the SAMPA v2 digital supply line current during chromium- 53 irradiation. . . 48

32 Plot of the SAMPA v2 digital supply line current during chromium-53 irradiation. . . 49

33 The control GUI of the Pulsys laser system. . . 51

34 The irradiation chamber of the Pulsys laser system. . . 52

35 Laser irradiation scan of the SAMPA v2 sensitive area. 1µm resolution. . . 56

36 Laser irradiation scan of the SAMPA v2 sensitive area. 500 nm resolution. . 56

37 Substrate location of the SAMPA v2 automatic scans.. . . 57

38 Single even latch-up threshold of the SAMPA v2, plotted against supply voltage. . . 57

39 Substrate surface of SAMPA v4.. . . 58

40 Substrate surface of SAMPA v2.. . . 58

41 The bare IDE3466 die. . . 62

42 Circuit diagram of the IDE3466 SELDM. . . 63

43 Block diagram of a typical SELDM application. . . 63

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List of Figures

44 IDEASlaboratory equipment used to interface the IDE3466. 1: LabFEC board, 2: power supply, 3: cable for LU-flag, 4: cable for SPI, 5: Pi, 6: SELA

and SELB connection, 7: RADEM test-board with ROIC. . . 64

45 Plot of shunt voltage versus supply sink current at each DAC step. . . 67

46 Plot of shunt voltage versus DAC step. . . 68

47 Flowchart describing the C++ program.. . . 69

48 Flowchart describing a single incremental loop within the C++ program. . . 69

49 Plot of sample delay caused by writing buffered data within the SELDM application. . . 71

50 Plot showing incremental, decremental and averaged current calculated by the SELDM application. . . 72

51 Plot showing effect of using rolling average on data from the SELDM application. . . 73

52 Delay caused by writing to file in the SELDM application, at approxiamtely 440 ms. . . 73

53 Software single event latch-up detection delay of the SELTC. . . 93

54 Propagation delay measured from SELB1 input to LU1 output.. . . 109

55 Propagation delay measured from SELB2 input to LU2 output. . . 110

56 Propagation delay measured from SELB1 input to (externally buffered) GLU output. . . 110

57 Propagation delay measured from SELB2 input to (externally buffered) GLU output. . . 111

58 Propagation delay measured from SPI CLK input to LU1 output. . . 111

59 Detection delay of the SELDM application’s single event latch-up check. . . 112

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List of Tables

1 Maximum energy for various particle species found in space. ©IEEE 2003

[25], reproduced with permission. . . 7

2 Spacecraft orbits and their relevant radiation environment. Altitude values from NASA’s Earth Observatory [39]. . . 8

3 Countermeasures against single event latch-ups.. . . 16

4 RHBD libraries . . . 18

5 Method for calculating the expected number of events from radiation hardness assurance test results . . . 22

6 Functional requirements for the single event latch-up test circuit. . . 26

7 Performance requirements for the single event latch-up test circuit. Samples per second are indicated by S/s. . . 26

8 Design requirements for the single event latch-up test circuit. . . 26

9 Operational requirements for the single event latch-up test circuit. . . 27

10 Main components of the final single event latch-up test circuit. . . 27

11 Specifications of the final single event latch-up test circuit. . . 29

12 Compliance matrix listing requirements either not fully verified or met by the current SELTC version. . . 30

13 Proposed revisions of the single event latch-up test circuit board. . . 30

14 Sampling rate measurements of the SELTC interfaced by a C++ program running on the Raspberry Pi SoC.. . . 32

15 An I2C read-operation’s CPU usage on the Raspberry Pi SoC measured using ticks. . . 32

16 Through-software SEL detection delay measurements of the SELTC. . . 32

17 Measures to reduce the supply line resistance of the SELTC. . . 36

18 University equipment used for SEE tests. . . 39

19 Voltage regulation on the SAMPA test-board.. . . 41

20 Difference in idle current draw during SEU tests performed the SAMPA v4 digital supply line. . . 42

21 Modifications done to Python program before performing radiation tests with the SELTC.. . . 42

22 Sampling rate using Python to log shunt and bus voltages of four SELTC channels. . . 43

23 Available particle cocktails at the UCL HIF. . . 44

24 Setup of the SELTC during heavy-ion test. . . 46

25 Results from heavy-ion test of the SAMPA v2 ASIC. . . 49

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26 Set-up of the SELTC for the laser test campaign. . . 52 27 Typical LDO settings for varying DUT supply during laser irradiation.. . . 53 28 Sampling rate after emitting various functions from the Python program. . 54 29 Laser system beam parameters used during ASIC irradiation. . . 54 30 Laser system parameters used during automatic irradiation scan of the SAMPA

ASIC. . . 55 31 Single event latch-up thresholds found during laser irradiation of SAMPA

ASICs.. . . 55 32 SELTC performance comparison of Python and equivalent C++ code. . . . 59 33 IDE3466 SELDM circuit parameters expected after simulation and design. . 62 34 Test equipment used for work with the IDE3466 ROIC. . . 64 35 Tests performed on the IDE3466 SELDM. . . 65 36 SELDM detection delay measurements. Outputτ denotes the time con-

stant of the digital transition. . . 66 37 Selection of IDE3466 SELDM characterisation values. . . 66 38 Current ranges of various shunt resistors, using the step voltage model found

through linear regression, and the simulated DAC step voltage. . . 67 39 The IDE3466 SELDM alternative application’s current measurement devi-

ation. DAC steps are denoted ass, shunt voltage slope asa, and shunt voltage bias asc. . . . 70 40 Parameters utilised in the IDE3466 SELDM application. . . 70 41 Tests performed to benchmark the SELDM current-logging application. . . 71 42 Current-logging application performance measurements . . . 72 43 Comparison of the 3D Plus LCL and the IDEAS IDE3466 SELDM. . . 79 44 Shunt voltage and supply current for each IDE3466 DAC step. . . 114

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I Introduction

This chapter presents the motivation for examining single event latch-up protection solutions, the main goal of the thesis and summaries of each chapter’s contents.

1 Motivation

Integrated electronic circuits¹are ubiquitous in modern electronics. Most circuit boards and systems contain a plethora of integrated circuits performing different functions. The growth of annual sales in the global semiconductor market is shown in Fig.1. As demands push prices and requirements these circuits evolve rapidly, increasing availability and application areas.

Generic integrated circuits are present in many harsh radiation environments on and around earth. Such environments and their particle radiation have been found to cause functional failures as well as permanent damage to semiconductor circuits². Therefore, understanding as to how radiation can cause damage and how to protect against failure becomes increasingly important.

19700 1980 1990 2000 2010 2020 100

200 300 400 500

Year

Sales [Billion USD]

Global Semiconductor Sales 1978-2017

Figure 1: Annual sales in the global semiconductor market. Plotted using data from SIA [13].

1Semiconductor circuits of high density, implemented using conductors and isolators on doped silicon.[1]

2See references [2,3,4,5,6,7,8,9,10,11,12] for an historical overview of such radiation effects

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2 Goal

Themain goal of this thesis is to explore single event latch-up protection circuits. The work will contribute to future projects intended to operate in harsh radiation environments developed by the University of Oslo (UiO). The first objective towards this goal is the development of a low-cost protection circuit. The circuit shall double as a single event latch-up test circuit, in order to simplify radiation tests performed by the university and its partners. The circuit was to be validated at 2 radiation test campaigns. The second objective is the verifi- cation and application of a single event latch-up protection circuit developed by Integrated Detector Electronics AS (IDEAS). This circuit is implemented in silicon using various radiation hardening techniques. It should therefore represent the high-end of protection circuits, both in terms of size, radiation tolerance and performance. Together, these two objectives will give insight into the variety of on-site single event latch-up protection circuits, providing a neutral perspective on single event latch-up protection for future circuit development at UiO and beyond.

3 Thesis Contents

ChapterIcontains the introduction to the thesis.

ChapterIIsummarises research on single event latch-up, providing a theoretical background for the rest of the thesis. In detail, the chapter covers the physical mechanisms behind single event latch-up, countermeasures of various abstraction levels, radiation test methods, and single event latch-up in relation to technology scaling.

ChapterIIIdocuments the production of a circuit board made mainly for testing the single event effects sensitivity of components. The board was used in the radiation tests of chapter IV.

ChapterIVpresents single event effects test campaigns performed to find the single event effects sensitivity and characteristics of an integrated circuit. The circuit-board documented in the chapterIIIwas used to detect and remove single event latch-ups.

ChapterVcovers work done with the IDEAS IDE3466 integrated circuit, and specifically the single event latch-up detection module it contains. Various parameters of the module are measured, before it is experimented with in a typical use case scenario, exploring its potential as a standalone commercial offering.

ChapterVIsummarises the work done during the master thesis, drawing an overall conclusion and discussing future possibilities.

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II Theoretical Background

This chapter will cover relevant theoretical material and research on single event latch-up (SEL) in electronic circuits. Acting as an introduction to the chapter, radiation effects in electronic circuits are summarised, followed by definitions relevant to particle radiation. Ra- diation environments, particle interaction and single event latch-up formation are then explained, before various countermeasures and sensitivity testing methods are evaluated. Tech- nology scaling and its relation to single event latch-up is discussed before concluding.

1 Radiation Effects in Electronic Circuits

Radiation effects are seen in electronic circuits hit by ionising radiation transferring energy to the circuit [14]. A circuit’s response to radiation varies greatly, both in terms of incident radiation and circuit type. Radiation effects are divided into cumulative and single event effects.

This thesis focuses on the single event effects, and specifically the permanent, potentially destructive, effect called single event latch-up.

1.1 Cumulative Effects

Cumulative effects consist of total ionising dose (TID) and displacement damage (DD) [15].

These effects worsen with increased exposure [15], making them especially relevant for pro- longed space missions. TID typically concerns trapped charges in transistor oxides [16], while DD typically concerns changes in the semiconductor crystal lattice as a result of non-ionising nuclear interaction [15]. These effects are actively prevented by shielding, and/or annealing i.e. baking the semiconductor at high temperatures [17,18].

1.2 Single Event Effects

Single event effects in electronic systems are caused by the interaction of an energetic particle with the system’s electronic components [19]. Single event effects (SEEs) are stochastic, as only a single particle is needed to induce an effect within a circuit. These radiation effects were discovered in the early 1970s [2,3,4], and are classified according to their consequence [20]. The top-level division is into non-destructive and (potentially) destructive SEEs [20].

Non-destructive SEEs, also called soft errors[5], are removable and do not cause permanent damage to the circuit [5]. A common non-destructive SEE is single event upset (SEU), which results in logical bit-flips [21]. These bit errors are recoverable by rewriting the affected bit [21]. Common destructive SEEs are single event latch-ups, single event burnouts, single event gate ruptures and single event snapbacks [20].

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Single event latch-up occurs in complimentary metal-oxide semiconductor (CMOS) circuits hit by a single ionising particle [2,3,20,22]. Today, 98 percent of newly designed digital systems utilise a CMOS process [1]. The consequence of single event latch-up in CMOS circuits can be thermal failure and/or localised metal fusion [20], eventually leading to non- functional components and system failure [6,7,8]. The following particles can theoretically trigger latch-up [23,24]: heavy ions i.e. alpha particles, protons, neutrons, and high-energy photons. As CMOS technology is widespread, and these particle types exist in many environments [25,26], single event latch-up is a phenomenon important for engineers to understand and counteract. Single event latch-ups are further explained in section5.

2 Particle Radiation

According to Knoll [27] we can divide particle radiation into two, "charged particulate radiation" and "uncharged radiation". Each of these contain two subcategories, "charged particulate radiation" containing fast electrons and heavy charged particles, and "uncharged radiation" containing neutrons and electromagnetic radiation. This thesis will focus on heavy charged particles, as these are especially capable of triggering single event latch-ups. How heavy charged particles trigger single event latch-up will be described in section5. Knoll [27]

is the main source of the material presented in this section.

2.1 Energy Units

A particle’s kinetic energy is usually defined by the unit electron volt, or eV. Electron volts are equivalent to Joules (1 eV = 1.602·10⁻¹⁹J). The energy of one 2e charge alpha particle accelerated by a 1 V-potential equals 2 eV. Radiation energies up to several GeV are common in space scenarios, as will be shown in section3.2. Fig.2from Stassinopoulos [28] shows the kinetic energies needed to penetrate Earth’s magnetosphere.

2.2 Heavy Charged Particles

According to Knoll, heavy charged particles include all energetic ions with mass of one atomic mass unit or more. This includes protons, alpha particles, fission products, as well as products of many other nuclear interactions.

2.3 Neutrons

Neutrons are often divided into slow and fast neutrons. Slow and fast defines the kinetic energy of the neutron, with slow being below a few eVs, and fast up to hundreds of MeVs.

Thermal neutrons are an example of slow neutrons. A thermal neutron is slowed down, or "thermalised" by a moderator to a kinetic energy of 0.025 eV. Even at this kinetic energy, the thermal neutrons can cause excitation within an absorber: when irradiated by thermal neutrons, a boron-10 absorber will decay into lithium-7 and an alpha particle. The kinetic energy of this alpha particle can be 1.47 MeV, or higher if lithium-7 reaches its ground state.

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3 Radiation Environments

Figure 2: Illustration of the particle energies needed to penetrate the Earth magnetosphere. ©IEEE 1988 [28], reprinted with permission.

3 Radiation Environments

One can divide the natural radiation environments into terrestrial, atmospheric, and space [25,28]. Human made radiation environments are called artificial environments, and include the particle accelerator like that of the Large Hadron Collider (LHC) at CERN (Con- seil Européen pour la Recherche Nucléaire) [29]. The radiation environment of the LHC is known to induce single event effects in standard, COTS (Commercial Off The Shelf) components [30,31]. Almost all radiation environments contain either neutrons or heavy-charged particles [25,30]. Different environments contain different types of particle radiation species [25], and some are therefore more prone to trigger latch-up in circuits than others [32]. This necessitates considering the intended environment when working with electronics. Inter- planetary space and Earth’s inner radiation belt are two examples of radiation environments containing an abundance of particle radiation [32], and consequentially, both environments have been found to cause system failures in the past [8].

3.1 Atmospheric & Terrestrial Environments

Particle radiation seen at ground level is mainly the remainder of energetic particle precipitation [25,26]. Fig.3taken from Barth [25] shows particle precipitation and its decay. Heavy charged particles passing Earth’s magnetic field are usually deflected or trapped within it, but some particles manage to enter the atmosphere. These particles, mainly galactic cosmic rays (GCRs) and at times solar energetic particles (SEPs), decay or slow down when interacting with atmospheric particles [25], resulting in heavy ions, protons, neutrons, electrons, pions, and muons. As a result, the charge and mass of these particles decrease during their descent.

Before reaching ground level, the particle precipitation will reach an altitude where the rate of ionising particles is at a maximum, known as the Regener–Pfotzer maximum [33], located

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at approximately 20 km. The atmospheric radiation is especially relevant to commercial and military aircraft, and has been found to cause data error in airborne circuits [34]. When the precipitation reaches ground level, its particles have experienced 6-7 interaction generations, and most of them have decayed into low-mass particles, like neutrons [26]. As previously mentioned in section2.3, neutrons can interact with absorbers, causing them to emit particles of notable kinetic energy. As a result, neutrons are capable of triggering single event effects in electronic circuits [10,24,35]. This emphasises the importance of testing electronics for the ground level radiation environment too, even though few directly ionising particles are present. Indeed, the first research paper [36] mentioning radiation induced failures in electronics predicted that terrestrial cosmic rays would infer a limitation on the packing density of semiconductor devices.

Figure 3: Energetic particle precipitation in the Earth atmosphere creating neutrons at ground level.

©IEEE 2003 [25], reprinted with permission.

3.2 The Space Environment

For simplification, the term space will here include all environments from orbital to interstel- lar space. The flux of various particles (1≤Z ≤28) in near-earth space is plotted in Fig.4.

Note that high-energy particles are rare, while low-energy particles are common. Maximum particle energies found in the space environment [25] are listed in Tab.1.

GCRs and SEPs in the Earth magnetosphere see the magnetic field act upon them due to the Lorentz force [25]. Some of these charged particles are trapped by the magnetic field [28], creating radiation belts also known as Van Allen belts, shown in Fig.5. The centre of the inner belt is located at approximately 2500 km above sea level, while the outer belt is at

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3 Radiation Environments Table 1: Maximum energy for various particle species found in space.©IEEE 2003 [25], reproduced

with permission.

Particle Type Maximum Energy

Trapped Electrons 10’s of MeV

Trapped Protons & Heavy Ions 100’s of MeV

Solar Protons ~GeV

Solar Heavy Ions ~GeV

Galactic Cosmic Rays ~TeV

10⁰ 10¹ 10² 10³ 10⁴ 10⁵

Kinetic Energy (MeV/nucleon) 10^-9

10^-7 10^-5 10^-3 10^-1 10¹ 10³

Flux (m2 -s-sr-MeV/nuc)-1

1-H 4-He 12-C 14-N 16-O 56-Fe

Figure 4: Simulation of particle fluxes in near-earth (interplanetary) space at maximum solar activity. Made using CREME96 [37,38], which accounts for trapped protons, solar energetic particles and cosmic rays.

approximately 20000 km [25]. The inner belt is dominated by protons, and the outer by electrons as shown in Fig.5. Usually, satellite orbits are classified according to altitude, see Tab.2which shows the division into low earth orbit (LEO), medium earth orbit (MEO) and high earth orbit (HEO) [39].

As a result of the misalignment of Earth’s magnetic dipoles, and rotational axis, the in- nermost Van Allen belt is notably closer to ground level over South America [25]. This area, which contains an unusual amount of particle radiation for its altitude, is known as the South Atlantic Anomaly (SAA) [41]. In the area proton rich radiation is found at altitudes as low as 200 km, according to SPENVIS [42] and the utilised "AP8" model. As a result, LEO satellites travelling through the anomaly see single event-related failures in disproportionate numbers [8,41]. When protons interact with matter, nuclear collisions can create secondary particles capable of large energy transfers, further described in section5. A SPENVIS [42] simulation of the flux of protons at 500 km altitude is shown in Fig. 7, illustrating the South Atlantic Anomaly. The simulated altitude of 500 km is approximately the altitude of the Interna- tional Space Station in LEO [43].

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Table 2: Spacecraft orbits and their relevant radiation environment. Altitude values from NASA’s Earth Observatory [39].

Orbit Altitude Environment Particles

LEO 180-2000 km Inner belt & SAA Trapped p⁺& e⁻ MEO 2000-36000 km Van Allen belts Trapped e⁻& p⁺ GEO ≈36000 km Solar rays, GCR e⁻, p⁺, heavy ions

Figure 5: Illustration of the Van Allen belts present around Earth. Picture from NASA’s Langley Re- search Center [40].

The main source of radiation in our solar system is the Sun, and its intensity varies with an approximate cycle of 11 years [44]. In addition to the solar radiation, GCRs of high kinetic energies originating from outside the solar system are also present. Within the heliosphere, the GCRs are found to be anti-correlated with the solar activity because of the Sun’s proxim- ity [25]. This effect can be seen in Fig.6from Bourdarie [44].

Figure 6: Observed variation in cosmic ray particles, caused by solar activity. ©IEEE 2008 [44], reprinted with permission.

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4 Stopping Power

Figure 7: Flux of protons withE^kin≥10MeV at 500 km altitude, generated with SPENVIS [42].

4 Stopping Power

A heavy charged particle entering an absorber transfers energy to it through interaction with the absorber electrons and nuclei [27,45]. In integrated circuits (ICs), the absorber is usually silicon crystal in addition to conductors and dielectric materials [46], where the dielectric can contain the previously mentioned neutron-sensitive boron. Researchers have worked with particle interaction since the turn of the 20th century. Bohr [47], Bethe [48], Bloch [49]

and Fermi [50] provided the basis needed for today’s models and calculations of particle interaction. Stopping power, as shown in the Bethe-Bloch formula [27] of Eq. 1, represents an ionising particle’s rate of energy loss along its path, either by means of excitation and ionisation of the absorber medium [27,48]. Particles with a higher chargeZ exhibit a larger stopping power due to increased ionisation. Particles of higher kinetic energyE_kin, or veloc- ityv, will exhibit a smaller stopping power due to the reduced duration of the interactions and ionisation. When the incident particle has been slowed down to a low veloctiy, it will start exchanging charges with the absorber medium, making other stopping forces like non- ionising energy loss (NIEL) and secondary reactions more prominent [27]. The Bethe-Bloch is therefore imprecise at lower particle energies [27].Nrepresents the density of the absorber, whileAis the absorber’s atomic number. With exception ofA, the expression for the scalar Bis only evaluated for relativistic particles. The unit for the incident particle’s kinetic energy is MeV, or MeV/amu if divided by the particle’s atomic mass [51]. Stopping power,Sis declared in units of MeV/cm, or MeV·cm²/mg if divided by the absorber’s density [27].

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S=−dE

dx = 4πe⁴Z²

m₀v² N B (1)

where

B ≡A[ln(2m0v²

I )−ln(1−v² c²)−v²

c² ] and

S∝ z

v² given the same absorber.

4.1 Linear Energy Transfer

The rate of energy transfer can also be denoted as linear energy transfer (LET) [52], also known as electronic stopping power [53]. LET is often utilised in stead of stopping power when describing heavy charged particles that cause single event effects [54,55,56], as it is almost equal to the energy that generates electron-hole pairs within the absorber [57]. As defined in Eq. 2, LET is the linear rate of energy deposited within the absorber. Alinear energy transfer will disregard other stopping forces like non-ionising energy loss (NIEL) and secondary reactions [27,58], and LET therefore excludes some of the stopping forces. The perspective of something being deposited within the absorber is often more convenient than traditional stopping power, especially when using silicon detectors.

LET =|S|= dE

dx is the linear energy transfer. (2) where

LET ∝ z

v² given the same absorber.

⇒ less kinetic energy per nucleon yields larger LET.

4.2 Modelling Tools

LET is often calculated with models using the particle’s incident kinetic energyE_kin, charge Zand atomic numberA, together with the properties of the absorber medium [53]. Ex- amples of models utilising data records together with stopping theory are SRIM [59], the NIST databases [60], and MSTAR [61,62]. There has been uncertainty in the calculations of these models, both for heavier particles [53], and lower incident kinetic energies [63]. At lower kinetic energies, the particle will start recombining with the absorber, reducing energy lost through ionisation. Consequently, NIEL will become more prominent at lower energies [58]. Fig.8shows a the calculation of LET with a relatively new model by Javanainen [64].

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5 From Irradiation to Single Event Latch-up Thedata correlate with the Bethe-Bloch formula at higher energies and down until some MeV/amu, where they reach the Bragg peak¹and the LET decreases due to recombination.

Figure 8: LET in a carbon absorber as a function of the incident particle’s kinetic energy. Irradiated particles from top to bottom: xenon, krypton, argon, oxygen and helium. ©2012 Elsevier [64], reprinted with permission.

5 From Irradiation to Single Event Latch-up

A particle’s capability to trigger single event latch-up is dependent on the number of excess charge carriers it releases within the silicon substrate [20]. The number of generated electron- hole pairs corresponds with the energy transferred to the circuit. In silicon, the energy needed to generate one electron-hole pair, also known as the ionisation energy, is approximately 3 eV [27]. Ergo, a higher LET throughout the charged particle’s interaction, i.e. xenon in the previously shown Fig.8, indicates a greater capability to trigger single event latch-ups.

5.1 Neutrons and Protons Triggering Latch-up

It is tempting to draw the conclusion that neutrons will not be able to trigger latch-ups, as neutrons have no charge. The same is true for protons as their mass is small compared to heavier ions. However, neutrons [6,24] as well as protons [67] have been found to trigger latch-up in integrated circuits. Even thermal neutrons with their minute kinetic energies have been found to trigger single event effects when interacting with boron-10 inside integrated circuits [68]. Instead of direct ionisation, these particles indirectly ionise the absorber through

1The peak of the Bragg curve, a plot of the stopping power versus penetration depth [27,65]. The Bragg peak is utilised extensively by proton therapy [66].

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secondary particles emitted by inelastic nuclear collisions [10,69,70]. The secondary particle can be an alpha particle, and thus a charge-less particle like a neutron is able to cause a single event latch-up in a circuit. Increasing incident angle is found to increase the the probability of single event latch-ups when irradiating protons [6,71]. Increasing the incident angle lengthens the particle track, and thus, the probability of a nuclear collision.

The probability of single event latch-up, or cross section, from protons has been found to be approximately10⁻⁵ as compared to heavy ions [72]. As shown earlier, protons and other light particles are more prominent in the natural radiation environments than heavier ions. Fig.4’s simulation found H-1 ions, or protons, to be of approximately10⁴higher flux than Fe-56 in the near-earth radiation environment. An even more proton-rich environment like the inner Van Allen belt should see the difference in proton flux compared to heavy ions surpass the difference in cross section. If this is the case, the number of proton-triggered latch-ups will surpass that of heavy ions.

5.2 Single Event Latch-up Formation

The formation of a single event latch-up in a bulk CMOS circuit is described chronologically in the list below [20,23,73]. The particle’s (direct or indirect) interaction with (n-well, bulk CMOS) silicon substrate, leaving electron-hole pairs is shown in Fig.9. After the ionisation, a single event latch-up has the same characteristic as a traditional latch-up [23,73], which can be triggered by other means such as electrostatic discharge (ESD). To understand single event latch-up better we will look at both the triggering and the latched "thyristor" operation that follows. The parasitic bipolar junction transistors (BJTs) that create the thyristor is shown in Fig. 10, and the equivalent circuit diagram when the CMOS is connected as an inverter in Fig. 11. A CMOS inverter [1] connects the n-channel MOSFET’s (NMOS) source and body to the negative rail (V_SS), and the p-channel MOSFET’s (PMOS) source and body to the positive rail (V_DD).

Figure 9: Cross section of CMOS structure irradiated by ionising particles. One NMOS (left) and PMOS (right) device shown.

The single event latch-up occurs as follows:

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5 From Irradiation to Single Event Latch-up 1. An incident particle irradiates the silicon of the CMOS substrate, generating electron-

hole pairs along its path.

2. If the device is powered, the electron-hole pairs will flow towards the positive and negative voltage rails as dictated by their polarity.

3. The charges travel through pn-junctions within the substrate on their way to the supply rails.

4. If the current is large enough, parasitic BJTs will be biased, effectively turning on a parasitic thyristor, seen in Fig.10and11.

5. The result is a low-impedance current path acting as a short between the voltage rails, limited in theory only by the resistances within the substrate.

6. If the voltage rails is larger than the thyristor "holding voltage" the BJTs will draw large currents, increasing the dissipated power in both substrate and conductors, potentially leading to thermal failure.

Figure 10: Parasitic BJTs present in a CMOS structure. One NMOS (left) and PMOS (right) device shown. Adapted from Shoga & Binder [74].

5.3 Thyristor Operation

Thyristors have been used since the 1950s in high-current switching applications [75,76], and are also known as PNPN diodes, or silicon-controlled rectifiers. A circuit diagram of the parasitic thyristor present in CMOS technology is shown in Fig. 11. In this configuration, the NMOS transistor is referenced toV_SSand PMOS transistor toV_SS. If one removes the resistances from this circuit it represents the ideal thyristor.

The current-voltage characteristics of an ideal thyristor is shown in Fig. 12by Hargrove [77]. The thyristor works in a regenerative fashion [73], with the accumulated current of one transistor feeding into the base of the other and then amplified by the respective gainβ. The connection acts as a short betweenV_DDandV_SS, as long as the BJTs are biased in saturation

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VDD

R_NWELL

R_PSUB V_SS

Figure 11: Parasitic thyristor in n-well CMOS, with high and low potential connected through PMOS and NMOS transistors. Adapted from Troutman [73].

[73]. The voltage drop needed to bias the BJTs is shown by the dashed lines fromV_StoV_H in Fig.12’s plot. When the circuit is biased leading, the current will rise to its maximum. It is found that biasing only one of these pn-junctions fully is sufficient to accomplish a latch-up [72], meaning the holding voltage can be smaller than two pn-junction drops. The holding voltage of the parasitic thyristor in bulk CMOS has been found to be as low as 1 V at room temperature [78].

5.4 Micro Latch-ups

In larger integrated circuits, single event latch-ups can happen in separate parts of the circuit [72]. Single event latch-ups happening in the various locations, can each increase the current in a latched state. If the thyristor current of these circuits are limited by the power supply, or countermeasures alike those listed in section6are used, then the total current can be found to increase with discrete steps for each single event latch-up [79]. These events, represented by discrete current steps, are called micro latch-ups [79,80]. Micro latch-ups have been found to correlate with bursts of SEUs when occurring in memory circuits [79].

6 Countermeasures

Countermeasures against single event latch-up distinguished by the level at which they are in- troduced [73,81]. Process countermeasures are implemented by altering the semiconductor production process; layout countermeasures are implemented by altering the design of the

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6 Countermeasures

Figure 12: Current-voltage characteristic of a PNPN junction, representing the ideal thyristor without substrate and well resistances.©IEEE 1998 [77], reprinted with permission.

integrated circuit; system countermeasures are implemented with an already produced circuit within the intended system. A selection of countermeasures are listed in Tab.3. Most of these bring with them an area and/or cost increase. The effective and often recommended solution [23,73] of combining guard rings in layout with an epitaxial layer process is illustrated in Fig. 13by Hargrove [77], where minority charge carriers are deterred by an underlying, highly doped substrate and/or collected by a guard ring.

Figure 13: N-well minority carrier guard ring collecting charges in bulk (top) and epitaxial layer (bottom) CMOS.©IEEE 1998 [77], reprinted with permission.

6.1 Process Level Latch-up Countermeasures

Process countermeasures usually aim to mitigate latch-ups by decoupling the free charge carriers from the parasitic BJTs [3,73]. The exception to this is diffusion [73], which rather aims to spoil the gain of the BJTs. Diffusion is not used much at modern production nodes as it affects performance [73]. Circuits implementing process-level countermeasures are called ra-

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Table 3: Countermeasures against single event latch-ups.

Technique Implementation Explanation Ref.

Silicon-on-insulator Process Use instead

of bulk CMOS. [82,83]

Epitaxial Process

Decouple BJTs with thin epitaxial layer on highly doped substrate.

[73,84]

Diffusion. Process

Spoil BJT gain by reducing carrier lifetime.

[73]

Trench Process Isolate p- and n-channels

with dielectric trench. [77]

Guard rings Layout

Provide low-impedance path to supply voltage for charge carriers.

[73,83]

Spacing Layout Increase transistor spacing,

lowering BJT gain. [23]

IC watchdog Layout/system

Integrated monitoring of rail, de-latching if current is larger than threshold.

[85]

PCB watchdog System

Monitoring IC supply, de-latching if current is larger than threshold.

[11,20]

Temp. decr. Process/layout/system Reduce heat/power. [74,86]

Supply decr. Process/layout/system Design forVsup< V_holding. [24,77]

diation hardened by process (RHBP). Generally, process-level countermeasures increase fabrication cost, especially the silicon-on-insulator process which is 10-15 percent costlier than CMOS [81]. It is worth mentioning that the effectiveness of process-level countermeasures are dependent on the specific CMOS technology, and how these scale [87] which is discussed further in section8

An example is the epitaxial layer, a thin, lightly doped silicon layer deposited (by means of epitaxy) on a highly doped substrate [88], where semiconductor circuit’s can be implemented. The highly doped substrate below the layer can act upon charge carriers in the epitaxial layer, e.g. deterring minority charge carriers [73]. The thinness of the epitaxial layer should also lead to a lower energy transfer, on account of fewer interactions within the epitaxial layer and thus circuit. It is also worth mentioning that an epitaxial layer increases the thyristor holding voltage [72,77], meaning the parasitic thyristor needs a larger voltage to be

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6 Countermeasures biased leading. The effect of implementing an epitaxial layer on holding voltage is shown in Fig.14from Johnston [72]. All of these properties should be beneficial against single event latch-up, making the epitaxial wafer a recommended process-level countermeasure [3,89].

Figure 14: Thyristor holding voltage as a function of anode-to-cathode (NMOS-to-PMOS) spacing for different epitaxial layer thickness.©IEEE 1996 [72], reprinted with permission.

6.2 Layout Level Latch-up Countermeasures

Layout techniques alter the integrated circuit’s topology, mainly to lead charges away from the parasitic thyristor [73]. Circuits using these techniques are called radiation hardened by design (RHBD). RHBD libraries maintained by various companies are listed in Tab.4.

A common RHBD technique used against latch-up are guard rings [73,46], which were illustrated in Fig.13. A guard ring contact makes the driving potential available in the substrate and/or well. By collecting the free charge carriers, less current is available for the parasitic thyristor and its BJTs, reducing the chance of latch-up. Implementing guard rings increases the area of the integrated by 10-15 percent [81] and as a result, the cost. If implemented on an epitaxial layer, guard rings are even more effective [77]. As previously shown in Fig.13, the highly doped substrate will deter minority carriers, leading them to the guard rings within the thin, epitaxial layer. Another layout-level countermeasure is to increase the anode-to-cathode spacing [72]. In addition to lowering the BJT gain, this increases the holding voltage of the parasitic thyristor, as seen in Fig.14by Johnston [72].

6.3 System Level Latch-up Countermeasures

Finding components that are designed, tested and qualified for harsh radiation environments is not always easy, especially not within budget. Using COTS components instead will create the need for system-level latch-up countermeasures. System-level countermeasures typically monitor the supply current for large values, and power cycle once a high-current state (latch- up) is detected [20]. This will turn off the thyristor’s BJTs. Such circuits are known as watch-

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Table 4: RHBD libraries

Organisation Library Ref.

ESA DARE (0.18um) [90]

CERN 0.25um for LHC [91]

IDEAS 0.35um CMOS [92,93]

BAE 0.15um [94]

Ramon 0.18um & 0.13um [95]

Cobham 600nm-90nm [96]

Microchip

MH1RT (0.35um), ATC18RHA (0.18um), ATMX150RHA (0.15um SOI)

[97]

ATK 0.35um [98]

ST Micro 65nm [99]

dog circuits and can be implemented with various discrete components [11,20] as shown in chapterIII, or as a single integrated circuit [85,100] as discussed in chapterV. Together with radiation hardness assurance testing, this countermeasure method represents a flexible and low-cost solution to single event latch-up. Typical systems can be low-cost such as CubeSats.

It should be noted, that while this technique can be sufficient to remove high-current latch- ups, there are some drawbacks. In complex integrated circuits [72], the current draw depends on which modules are in use. As a result, the current may increase in smaller, discrete jumps, called micro latch-ups [79], making single event latch-ups difficult to detect [72]. It’s therefore an advantage if the component has multiple supply pins, making individual latch-up thresholds possible. It is also an advantage if the monitored lines have a regulator indepen- dent of the watchdog circuit. If not, voltage drops from the increase in current can turn off the monitoring circuit, leaving the system unprotected. Another downside to this type of countermeasure is the possibility of latent damage to the monitored component, caused by undetected latch-ups or latency in the latch-up removal [11]. This is described further in section7.6.

6.4 Temperature and Supply Voltage

Two important single event latch-up countermeasures are adjustments to temperature and supply voltage. In order to lower single event latch-up sensitivity, both temperature [74,86]

and supply voltage [70,78] may be decreased. Decreasing temperature will lower the current gain of the circuit’s parasitic BJTs [1], thus increasing latch-up formation time and decreasing maximum current. Temperature effects on single event latch-up sensitivity are shown in Fig.

15from Sexton [20] under section7.

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7 Radiation Hardness Assurance Testing of Electronic Components

Decreasing the supply voltage will decrease the capability of the circuit to push and maintain the latched current through the parasitic thyristor. If the supply is below the thyristor holding voltage in bulk CMOS, found to be approximately 1.1 V at room temperature [78], single event latch-up should in theory disappear. Lowering either can be done by changing the process, layout or system set-up. For example, updating the process technology node of a specific circuit will see a decrease in both supply voltage and power usage [46,87], with temperature most likely following.

6.5 Remarks on other Radiation Effects

Many of the aforementioned countermeasures will alter a circuit’s response to other radiation effects as well. Depending on the type of system, radiation environment and mission duration a system will be susceptible to some effects more than to others. One has to prioritise protecting against radiation effects that will pose the largest risk. For instance if one considers TID or DD to be the biggest concern, it would not be advisable to add dielectric isolation like that of a silicon-on-insulator or trenches, as these trap charges and thus increase the total ionising dose [82,101]. If non-destructive SEEs like SEUs are a concern, one should not lower the supply voltage, as this will increase the SEU cross section [10,102], and thus increase the soft error rate.

7 Radiation Hardness Assurance Testing of Electronic Components

The sources used for this section are Schwank [103] for heavy ion tests, the European Co- operation for Space Standardisation (ECSS) [54,104] for test methods, and Dodds [71] for proton irradiation tests.

Radiation sensitivity of a circuit is tested by irradiating the circuit with particles of types and energies either adhering to test standards [54,104], or of similar energy transfers as the intended environment. The circuit is then monitored for effects, registering deviation from the expected circuit behaviour. In the case of SEE tests, the irradiating particles are typically protons or heavy ions. Heavy ions are usually characterised by LET, while protons are usually denoted by kinetic energy. As previously mentioned, LET is usually calculated with uncertainty, and this is also true for the LET reported by the test facilities [105]. Typical heavy ion flux used during SEE testing 10⁴-10⁶particles/cm²s [103,56], while examples of heavy ion LET values are 1 to 60 MeV·cm²/mg [55,56]. When testing standard, COTS components, one should note that different batches of components may see different radiation test results [106], as different processes yield slightly different circuits on account of wafer variations.

7.1 Single Event Latch-up Monitoring

Testing for single event latch-ups, the most common monitoring method is to measure supply line current, and classify currents above a threshold as events. The supply line must be power-cycled at these events, turning off the driving potential of the parasitic thyristor. It is important to measure the total circuit dead time, as the particles irradiated during this period

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should be removed from the sensitivity calculation [72]. One should also test the circuit at the maximum operating temperatures expected during the system’s lifetime, as higher temperatures increase the circuit’s latch-up cross section. This was shown in Fig.15from Sexton [20].

7.2 Cross Section Calculation

The goal is a graph of the circuit’s sensitive area as a function of energy, as shown in Fig.15 from Sexton [20]. The sensitive area is called the cross sectionσ, and has the unit cm². The cross section indicates the probability of an event at the respective energy. The circuit is irradiated with a flux of particles while recording all events. At each energy value, the number of events together with total number of irradiated particles, or fluence, provide the basis of the cross section at the respective LET, as shown in Eq.3. If few cross section measurements are made at each LET, one should include the counting error as shown in Eq.4[27]. The location of a particle within a particle beam is random [27], therefore the empiricalσis the cross section’s expectation value. If several cross section measurements are made at each LET, one should rather include the standard deviation of the measurements [105]. From the cross section graph one can extract two parameters used to characterise a circuit’s single event effect sensitivity [20,103]: the LET_thr, which denotes the LET at which the circuit stops experi- encing the SEE, andσsat, the saturation cross section, which denotes the maximum cross section found during the test. The cross section graph will asymptotically approach both these values, as shown in Fig.15.

σ(LET) = n_SEE

F cm² ± σ_e (3)

where σ_e= 100·

s (

√n_SEE nSEE

)²+ (

√F F

2

% is the counting error (4)

andFis the fluence, or number of irradiated particles. (5)

7.3 LET as a Function of Incident Angle

Changing the angle of incidence is found to increase the cross section when irradiating with heavy ions [71,107]. Consequently, altering the incident angle is used during radiation hardness assurance tests to increase the "effective LET" of heavy ions [103]. Calculating this effective LET is traditionally done by multiplying the calculated, vertically incident LET with its increased particle track [108], as shown in Eq.6. Golke [108] also points out that this Eq.

is only valid when the particle terminates outside the main substrate, for example for thin substrates like an epitaxial, or smaller incident angles. If this is not the case, one should use a more complex Eq. one to avoid errors. Schwank [chwank_radiation_2013] recommends limiting the incident angle to 45^◦

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7 Radiation Hardness Assurance Testing of Electronic Components

Figure 15: Typical latch-up sensitivity curve plotting cross section as a function of heavy-ion LET.

LET_eff = LET

cosθ (6)

whereθis the angle referenced to vertical irradiation 7.4 Calculating Expected Events in an Environment

After the cross section characteristic is found, it is possible to calculate the expected failures using freely available tools [37,42,109]. This makes it possible to determine whether the circuit is suited for the a certain environment. A method for calculating the expected number of events is listed in Tab.5. As the cross section curves found from radiation hardness assurance tests are discrete, and contain few values, they are usually fitted. The Weibull-distribution is often used for this purpose [105], but it can also be fitted to a log-normal function [110]. As soft errors is possible to correct by implementing error-correction code [111], one may tol- erate such failures. On the other hand, one single event latch-up can be sufficient reason to replace the component or system, because of its destructive nature.

7.5 Laser Radiation Testing as an Alternative Method

In the 1990s a new radiation test method was developed [112,113,114], utilising a pulsed laser to generate charges within silicon. These pulses, lasting picoseconds [115], ionise the substrate through excitation of electrons beyond the band-gap energy [116] Once the electron- hole pairs are present, the circuit will respond as if it was irradiated by an ionising particle.

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Table 5: Method for calculating the expected number of events from radiation hardness assurance test results

# Method Tool Result

1 Beam-test σ-formula Sensitivity-vs-LET

2 Modelling SPENVIS [42] or CREME [37,38] Flux-vs-Energy 3 Modelling SRIM [109] or Bethe-Bloch Flux-vs-LET

4 Calculation Flux·Tmission Fluence-vs-LET

5 Calculation Convolution ofσ& fluence curves Expected events

The laser differs from classical beam tests in two aspects: firstly, it is capable of irradiating with sub-micrometer precision [113]. This makes it possible to locate the sensitive components within a circuit. Calculating the cross section of an energy can therefore be done by scanning the entire circuit and finding the sensitive area precisely. One would expect this to produce a result with smaller error than calculating the expected value from a particle beam.

Secondly, there has not yet been done as much research and modelling of laser interaction [117], therefore the energy of a laser beam is not as easily translated to a radiation environment. It is possible to empirically translate incident laser energy to LET, by finding the LET conversion factor [117,118]. This conversion factor needs data from both a laser and heavy ion test, using for example both threshold energies.

7.6 Latent Damage to Irradiated Circuits

If possible, a visual inspection with a microscope should be done of the integrated circuit after it has experienced single event latch-ups. The circuit’s metal traces can rapidly fuse together during latch-up events [11]. Single event latch-up can occur in areas of the circuit with conductors under-dimensioned for larger currents, leading to relatively large dissipa- tions of power. A microscopic image of metallisation damage found on conductors after a single event latch-up is shown in Fig.16from Becker [11]. The circuit was a processor with many possible latch-up paths, complicating single event latch-up monitoring. In order for such damage to occur, the circuit only needs to be in a latched state for a short period. Ac- cording to Becker’s experiments [11], such damage can form as quickly as 60µs, but also as slowly as 18 ms. Therefore, a test system with latency in its detection and power cycling may allow for permanent damage. Newer, more complex circuits further complicate this issue, as they enable latch-up currents of various sizes, or micro latch-ups [72,79].

8 Scaling and Future Trends

When technology processes scale in size, it affects the electrical & physical characteristics of circuits [87]. As a consequence, the response to ionising radiation is also affected. Under- standing radiation effects scaling is complicated, as not every feature of CMOS scales propor- tionally with technology size. scaling theory [87], each CMOS technology generation should see a doubling of transistor density. As a result, one expects [87] a 30 percent reduction of

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8 Scaling and Future Trends

Figure 16: Damage in metal layer of an integrated circuit after a single event latch-up of 2 A, seen as metal spheres on conductors.©IEEE 2002 [11], reprinted with permission.

gate delay, 50 percent reduction of switching power consumption, as well as a 30 percent decrease in lateral and vertical dimensions. Today, specialised transistor structures like FinFETs [119] complicate these technology node parameters.

Single event latch-up sensitivity is strongly influenced by these changes. For example, threshold and supply voltages decrease to maintain efficiency and performance [87,120], which should decrease the single event latch-up sensitivity, especially if the supply is lower than the thyristor holding voltage [20,24], as this should remove latch-ups. Reducing transistor size should also see the sensitive circuit area decrease, given the same circuit layout is implemented with a doubled transistor density. Charge collection depth should also decrease with the vertical scaling [121], reducing the number of collected charges in the substrate.

However, single event latch-up scaling is not necessarily that simple. The thyristor holding voltage is found to scale down with technology nodes [77], cancelling the advantage of supply voltage reduction. Modern CMOS technology nodes are usually defined by the min- imum distance between transistors [87], and manufacturers are therefore prone to prioritise lateral scaling. The vertical dimension, including isolation, well, and substrate might therefore not scale synchronously. Neither is it clear that an increase in transistor density will lead to smaller circuit areas. Rather, the tendency seems to be an increase in total transistor count and functionality, worsening single event latch-up sensitivity [72]. Denser circuits can also expect an increase in temperature, and following, an increase in single event latch-up sensitivity [74,86]. All of these properties make it challenging to predict single event latch-up as CMOS technology scales.

8.1 Scaling of other Radiation Effects

As mentioned above, threshold voltages decrease when technology scales [120]. This will increase leakage currents caused by the total ionising dose’s breakdown of gate oxides [122].

A decrease in technology size is found to increase single event upsets [102]. For example, a lower threshold voltages should increase SEU sensitivity, as fewer charges are needed to turn on the MOSFET and flip a bit [10,102]. In addition, increasing metallisation has been found to correlate with single event upsets [35]. Increasing a circuit’s complexity naturally tends to

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increase the number of metal layers, as well as bits within a circuit, and this could explain an increase in errors, however, one would expect the number of errors per bits to remain unchanged. The number of single event transients (charge pulses that travel through signal paths) are found to increase with operating frequency [123]. As gate delay is reduced for each technology node [87], it is reasonable to assume single event transients (SETs) increase as well.

9 Summary

Ever since humans started exploring space, we have gathered data on radiation and its effects on circuits and systems. The radiation environment in our solar system, and especially around Earth has proven to contain a significant amount of radiation. This radiation, even though it usually has little kinetic energy, is capable of inducing many kinds of failure modes.

After its introduction, CMOS circuits have been found to be vulnerable to radiation, even to neutrons on ground level. Some of the reason for this is that the internal structure of the CMOS substrate form a parasitic BJT circuit, equivalent to a circuit traditionally used for high-current switching. Free charges released by radiation can turn this circuit on, effectively shorting the power supply if its biased. Large amounts of power can then dissipate in substrates and conductors originally dimensioned for much smaller currents, leading to burn damage. After the smoke cleared, researchers found ways to protect against this incon- venient property of CMOS. Particles like neutrons are quite difficult to stop, and as a result, the protection methods either involve changing the technology process, or dealing with electron-hole pairs freed within the substrate. After decades of research, single event latch-up has become a well understood radiation effect in electronic circuits. However, as integrated circuits become more intricate in their design and architecture, understanding single event latch-up is made more challenging, creating the need for continued development in this field of research.

10 Conclusion

When developing systems for various radiation environments, implementing effective pre- ventive measures in an integrated circuit’s layout or fabrication process represents a costly option. Commercial demand for radiation-hard components is relatively low compared to standard COTS components. If COTS components are used, engineer’s need to understand radiation effects like single event latch-up, and how protect against them. For example, radiation tests are essential to ensure correct operation when using such components. After executing protection and testing, it is possible to produce low-cost radiation-hard systems.

The relative cost of radiation tests will be small if the system is to be produced on a large scale, and especially compared to launching a system sensitive to radiation. Solutions for single event latch-up protection circuits, intended both for radiation testing and system-level protection, are discussed further in this thesis.