Advanced Model Predictive Control Algorithm for Inverters as a Low-cost Solution in ZynQ

(1)

Advanced Model Predictive

Control Algorithm for Inverters as a Low-cost Solution in ZynQ

Bjarte Hoff PhD Candidate

FPGA-forum 2016

(2)

Outline

• Motivation and application

• System overview

• Cascaded model predictive control (MPC)

• Hardware setup

• Inner control loop implementation

• Outer control loop implementation

• Performance

• Conclusion

(3)

Motivation and application

• Renewable energy is connected to the grid using power electronics

• Performance of the energy conversion depends on the control algorithm

Available Renewable

Energy

Energy not captured

Captured Renewable

Energy

Energy to grid

Loss in converter DC

DC AC Power electronic converter

Transmission losses

(4)

Introduction to MPC

t t+1 t+2 t+3 t+4 t+5 t+6 t+7

Discrete time Horizon

Horizon

Horizon Horizon

Horizon

1 N

Iteration 1 Iteration 2 Iteration 3 Iteration 4 Iteration 5

2 1 2 {0,1}

1 min . *

. . ( ),

k

s t k G

∈ +

+

−

=

u y y

y u

Finite control set MPC

min ( ) 1 2

. . ,

,

T T

x

T

i i

T

i i

q x x Gx x c

s t a x b i

a x b i

= +

= ∈

≥ ∈





Continuous control set MPC

Finite number of solutions: Infinite number of solutions:

(5)

Two-level three-phase converter

R _a L _a L _r R _r

C u

R u

v r (t)

C DC

R DC

N _grid

R _b L _b L _s R _s v s (t)

R _c L _c L _t R _t v t (t)

C v

R v

N _LCL

C w

R w +

i _a (t) i _b (t) i _c (t)

i _r (t) i _s (t) i _t (t) i _DC (t)

DC-link Power electronic LCL filter Grid

(6)

Cascaded MPC

Outer control loop

(Grid current MPC)

Inner control loop

(Converter current MPC) Converter

Grid current reference

Converter current reference

Measurements

signals Gate

rst *

i i _abc * d d d 1 , 2 , 3

1 2 3

2 1 2 , ,

1 1 2 3

1 1

min . *

. . ( , , )

,

abc k

d d d

k k

s t A d d d

C

+

+ +

−

=

i y

x x

y x

1

1 1 1

1 min . 1

2 . . ,

,

k

T T T

k k k

lb ub

k

lb ub

k

H H g

s t

→ −

− − −

∆ → → →

−

→

∆ ∆ + ∆

∆ ≤ ∆ ≤ ∆

≤ ≤

u u u u

u u u

x x x

Outer control loop (CCS-MPC) Inner control loop (FCS-MPC)

(7)

Hardware setup

Voltage Source Converter – Main components

Analog signal processing Digital signal processing

filter LCL IPM

LEM ICU

LEM High voltage components

Three-phase grid

Interface

SCADA

APU

Interface

ZynQ

Comparators InterfaceADC

Input/User output

(8)

Cascaded MPC control loop

Processing System Programmable Logic

Human Machine

Interface Initialize

Read measurements

Compensate for delay Prepare system

matrices (Px, Qv) Prepare system

matrix H

^T

(Px+Qv-I

rst,ref

)

Convex optimization (Active set)

Set new converter current references

RAM1 FCS-MPC core

CCS-MPC hardware acceleration

Mult-Add

x16

Update PLL

(9)

FCS-MPC hardware acceleration

Processing System

Programmable Logic

Add FPU

XADC

Convert

to float Analog measurements

Analog inputs Multiply

Move

Operand A

Operand B

Working memory Read

RAM1

RAM2 Working memory

Write

Program controller RAM1

RAM2

Program memory Program

counter

AMBA Interconnect (GP AXI port 0)

Processor Core

Processor I/O Unit (EMIO)

IGBT output driver IGBT

IGBT gate signals MUX

Initialize

Aquire analog measurements

Add measurement gains and offset

Compensate for

computational delay Calculate all eight possiblities Compare with reference currents Choose the switch compination which gives lowest error

XADC IGBT

Input Algorithm loop Output

Loop end

Analog input

channels Transistor gate

signals

(10)

Single-precision floating-point format

• Seven different values are compared by decomposing the floating point number into bits

1-bit 8-bits 23-bits

Sign Exponent Fraction

31 30 23 22 0

Single-precision floating-point format

exp 127

( 1) ^sign 2 ^onent (1 )

decimal value = − ⁻ ⋅ fraction

(11)

FCS-MPC Firmware

PC Addr_RAM1B Addr_RAM2A Addr_RAM2B RAM1B_W RAM2A_W EN_mult EN_add EN_comp EN_i2f R_Data_B(2) R_Data_A(1) R_comp R_i2f R_mult R_add ADC_convst Load_PC D_out Instruction

0 31 1 1 1 00111110000000001001001000000000

1 32 2 1 1 01000000000000010001001000000000

2 33 3 1 1 01000010000000011001001000000000

3 34 4 1 1 01000100000000100001001000000000

4 35 5 1 1 01000110000000101001001000000000

5 36 6 1 1 01001000000000110001001000000000

6 37 7 1 1 01001010000000111001001000000000

7 38 8 1 1 01001100000001000001001000000000

8 39 9 1 1 01001110000001001001001000000000

9 40 1 10 1 1 1 1 01010000000101010011001000010000

10 21 2 1 1 1 1 1 1 00101010001000001011101000010000

11 22 3 2 1 1 1 1 1 00101100001100010011101000010000

12 23 4 3 1 1 1 1 1 00101110010000011011101000010000

13 24 5 4 1 1 1 1 1 00110000010100100011101000010000

14 25 6 5 1 1 1 1 1 00110010011000101011101000010000

15 26 7 6 1 1 1 1 1 00110100011100110011101000010000

16 27 8 7 1 1 1 1 1 00110110100000111011101000010000

17 28 9 8 1 1 1 1 1 00111000100101000011101000010000

18 29 10 9 1 1 1 1 1 00111010101001001011101000010000

19 30 10 1 1 00111100000001010000101000000000

20 1 1 00000000000000000000101000000000

21 1 1 00000000000000000000101000000000

22 11 1 1 1 1 1 1 00010110000100000110101000001000

23 12 2 1 1 1 1 1 00011000001000000110101000001000

24 13 3 1 1 1 1 1 00011010001100000110101000001000

25 14 4 1 1 1 1 1 00011100010000000110101000001000

26 15 5 1 1 1 1 1 00011110010100000110101000001000

27 16 6 1 1 1 1 1 00100000011000000110101000001000

28 17 7 1 1 1 1 1 00100010011100000110101000001000

29 18 8 1 1 1 1 1 00100100100000000110101000001000

30 19 9 1 1 1 1 1 00100110100100000110101000001000

31 20 10 1 1 1 1 1 00101000101000000110101000001000

COE-file to program the Firmware is

generated from Excel using a macro

(12)

CCS-MPC hardware acceleration

Programmable Logic Processing System

FPU – Multiply-Add x 16

Operand A x 16 Operand B x 16

Working memory Read

Program controller

OPA x 16

Processor Core

Processor I/O Unit (EMIO)

Result Program counter &

memory AMBA Interconnect (GP AXI port 1)

Working memory Write

OPB x 16

Multiply-add x16 Interface

HPS AXI 0

DMA* AXI

interconnect BRAM

controller DRAM interface

*Optional

(13)

Multiply-Add x16

Operand B

X

+

+ + +

+ +

+

^Result

(14)

DRAM Interface

-- Output BRAM clock DRAM_clk_out <= clka;

-- Output address

DRAM_addr_in <= addra(12 downto 6);

DRAM_addr_out <= addra(8 downto 2);

-- RAM selected for write operations

with (addra(13) & addra(5 downto 2)) select RAM_select <=

"00000000000000000000000000000001" when "00000",

"00000000000000000000000000000010" when "00001",

"00000000000000000000000000000100" when "00010",

"00000000000000000000000000001000" when "00011",

"00000000000000000000000000010000" when "00100",

"00000000000000000000000000100000" when "00101",

etc…

(15)

Xilinx Vivado – Block schematic screenshot

(16)

Computational performance

• Inner control loop (FCS-MPC):

• Outer control loop (CCS-MPC):

Analog to digital conversion

5 4

3 2

1 0

FCS-MPC

t [µs]

50 40

30 20

10 0 t [µs]

100 90

80 70

60 Init AXI-comm. PLL &

Ref. gen. Solve KKT system using LU-decomp.

(4 iterations)

(17)

Simulation results

Dead-time: 1µs Dead-time: 5µs

IGBT-based converter

SiC-based converter

(18)

Experimental results

DC AC

Programmable three-phase

AC source

Three-phase

rectifier DC filter capacitor and

load

Converter LCL filter Variac Grid

400V, 50Hz

(19)

Advanced Model Predictive Control Algorithm for Inverters as a Low-cost Solution in ZynQ